MPC8280 datasheet(39/1386 Pages) FREESCALE

39 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

xxxix

Contents

Paragraph

Number

Title

Page

Number

32.12.2

AAL1 CES TxBDs .................................................................................................. 32-40

32.13

AAL1 CES Exceptions ................................................................................................ 32-41

32.13.1

AAL1 CES Interrupt Queue Entry........................................................................... 32-41

32.14

AAL1 Sequence Number (SN) Protection Table ........................................................ 32-42

32.15

Internal AAL1 CES Statistics Tables........................................................................... 32-43

32.16

External AAL1 CES Statistics Tables.......................................................................... 32-44

32.17

CES-Specific Additions to the MCC ........................................................................... 32-44

32.18

Application Considerations.......................................................................................... 32-44

Chapter 33

ATM AAL2

33.1

Introduction.................................................................................................................... 33-1

33.2

Features .......................................................................................................................... 33-3

33.3

AAL2 Transmitter.......................................................................................................... 33-5

33.3.1

Transmitter Overview ................................................................................................ 33-5

33.3.2

Transmit Priority Mechanism .................................................................................... 33-6

33.3.2.1

Round Robin Priority............................................................................................. 33-6

33.3.2.2

Fixed Priority ......................................................................................................... 33-7

33.3.3

Partial Fill Mode (PFM) ............................................................................................ 33-7

33.3.4

No STF Mode ............................................................................................................ 33-8

33.3.5

AAL2 Tx Data Structures .......................................................................................... 33-9

33.3.5.1

AAL2 Protocol-Specific TCT................................................................................ 33-9

33.3.5.2

CPS Tx Queue Descriptor ................................................................................... 33-12

33.3.5.3

CPS Buffer Structure ........................................................................................... 33-14

33.3.5.4

SSSAR Tx Queue Descriptor .............................................................................. 33-16

33.3.5.5

SSSAR Transmit Buffer Descriptor..................................................................... 33-18

33.4

AAL2 Receiver ............................................................................................................ 33-19

33.4.1

Receiver Overview .................................................................................................. 33-19

33.4.2

Mapping of PHY | VP | VC | CID............................................................................ 33-20

33.4.3

AAL2 Switching ...................................................................................................... 33-21

33.4.4

AAL2 RX Data Structures ....................................................................................... 33-22

33.4.4.1

AAL2 Protocol-Specific RCT ............................................................................. 33-23

33.4.4.2

CID Mapping Tables and RxQDs........................................................................ 33-26

33.4.4.3

CPS Rx Queue Descriptors.................................................................................. 33-26

33.4.4.4

CPS Receive Buffer Descriptor (RxBD) ............................................................. 33-27

33.4.4.5

CPS Switch Rx Queue Descriptor ....................................................................... 33-28

33.4.4.6

SWITCH Receive/Transmit Buffer Descriptor (RxBD)...................................... 33-29

33.4.4.7

SSSAR Rx Queue Descriptor .............................................................................. 33-30

33.4.4.8

SSSAR Receive Buffer Descriptor ...................................................................... 33-32

33.5

AAL2 Parameter RAM ................................................................................................ 33-34

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