MPC8280 datasheet(57/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

lvii

Figures

Figure

Number

Title

Page

Number

16-10

CMX FCC Clock Route Register (CMXFCR) ................................................................... 16-14

16-11

CMX SCC Clock Route Register (CMXSCR) ................................................................... 16-16

16-12

CMX SMC Clock Route Register (CMXSMR) ................................................................. 16-19

17-1

Baud-Rate Generator (BRG) Block Diagram ....................................................................... 17-1

17-2

Baud-Rate Generator Configuration Registers (BRGCx)..................................................... 17-2

18-1

Timer Block Diagram ........................................................................................................... 18-1

18-2

Timer Cascaded Mode Block Diagram................................................................................. 18-3

18-3

Timer Global Configuration Register 1 (TGCR1) ................................................................ 18-4

18-4

Timer Global Configuration Register 2 (TGCR2) ................................................................ 18-5

18-5

Timer Mode Registers (TMR1–TMR4)................................................................................ 18-6

18-6

Timer Reference Registers (TRR1–TRR4)........................................................................... 18-7

18-7

Timer Capture Registers (TCR1–TCR4) .............................................................................. 18-7

18-8

Timer Counter Registers (TCN1–TCN4).............................................................................. 18-7

18-9

Timer Event Registers (TER1–TER4) .................................................................................. 18-8

19-1

SDMA Data Paths ................................................................................................................. 19-1

19-2

SDMA Bus Arbitration (Transaction Steal).......................................................................... 19-3

19-3

SDMA Status Register (SDSR) ............................................................................................ 19-3

19-4

SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM) ........................................... 19-4

19-5

IDMA Transfer Buffer in the Dual-Port RAM ..................................................................... 19-7

19-6

Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer

(Size = 128 Bytes) ............................................................................................................ 19-8

19-7

IDMAx Channel BD Table.................................................................................................. 19-15

19-8

DCM Parameters................................................................................................................. 19-18

19-9

IDMA Event/Mask Registers (IDSR/IDMR) ..................................................................... 19-23

19-10

IDMA BD Structure ............................................................................................................ 19-23

20-1

SCC Block Diagram.............................................................................................................. 20-2

20-2

GSMR_H—General SCC Mode Register (High Order)....................................................... 20-3

20-3

GSMR_L—General SCC Mode Register (Low Order)........................................................ 20-5

20-4

Data Synchronization Register (DSR) .................................................................................. 20-9

20-5

Transmit-on-Demand Register (TODR) ............................................................................. 20-10

20-6

SCC Buffer Descriptors (BDs)............................................................................................ 20-11

20-7

SCC BD and Buffer Memory Structure .............................................................................. 20-12

20-8

Function Code Registers (RFCR and TFCR) ..................................................................... 20-15

20-9

Output Delay from RTS Asserted for Synchronous Protocols ........................................... 20-18

20-10

Output Delay from CTS Asserted for Synchronous Protocols ........................................... 20-18

20-11

CTS Lost in Synchronous Protocols ................................................................................... 20-19

20-12

Using CD to Control Synchronous Protocol Reception...................................................... 20-20

20-13

DPLL Receiver Block Diagram .......................................................................................... 20-21

20-14

DPLL Transmitter Block Diagram...................................................................................... 20-22

20-15

DPLL Encoding Examples.................................................................................................. 20-23

21-1

UART Character Format ....................................................................................................... 21-1

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