MPC8280 datasheet(82/1386 Pages) FREESCALE

82 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxxxii

Freescale Semiconductor

Organization

Following is a summary and a brief description of the chapters of this manual:

•

Part I, “Overview,” provides a high-level description of the MPC8280, describing general

operation and listing basic features.

— Chapter 1, “Overview,” provides a high-level description of MPC8280 functions and features.

It roughly follows the structure of this book, summarizing the relevant features and providing

references for the reader who needs additional information.

— Chapter 2, “G2_LE Core,” provides an overview of the MPC8280 core, summarizing topics

described in further detail in subsequent chapters.

— Chapter 3, “Memory Map,” presents a table showing where MPC8280 registers are mapped in

memory. It includes cross references that indicate where the registers are described in detail.

•

Part II, “Configuration and Reset,” describes start-up behavior of the MPC8280.

— Chapter 4, “System Interface Unit (SIU),” describes the system configuration and protection

functions that provide various monitors and timers, and the 60x bus configuration.

— Chapter 5, “Reset,” describes the behavior of the MPC8280 at reset and start-up.

•

Part III, “The Hardware Interface,” describes external signals, clocking, memory control, and

power management of the MPC8280.

— Chapter 6, “External Signals,” shows a functional pinout of the MPC8280 and describes the

MPC8280 signals.

— Chapter 7, “60x Signals,” describes signals on the 60x bus.

— Chapter 8, “The 60x Bus,” describes the operation of the bus used by processors that

implement the PowerPC architecture.

— Chapter 9, “PCI Bridge,” describes how the PCI bridge enables the MPC8280 to gluelessly

bridge PCI agents to a host processor that implements the PowerPC architecture and how it is

compliant with PCI Specification Revision 2.2.

— Chapter 10, “Clocks and Power Control,” describes the clocking architecture of the MPC8280.

— Chapter 11, “Memory Controller,” describes the memory controller, which controls a

maximum of eight memory banks shared among a general-purpose chip-select machine

(GPCM) and three user-programmable machines (UPMs).

— Chapter 12, “Secondary (L2) Cache Support,” provides information about implementation and

configuration of a level-2 cache.

— Chapter 13, “IEEE 1149.1 Test Access Port,” describes the dedicated user-accessible test

access port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port

and Boundary Scan Architecture.

•

Part IV, “Communications Processor Module,” describes the configuration, clocking, and

operation of the various communications protocols that the MPC8280 supports.

— Chapter 14, “Communications Processor Module Overview,” provides a brief overview of the

CPM.

— Chapter 15, “Serial Interface with Time-Slot Assigner,” describes the SIU, which controls

system start-up, initialization and operation, protection, as well as the external system bus.

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