MPC8280 datasheet(9/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

2.4.2.3.1

Entire Cache Locking ........................................................................................ 2-20

2.4.2.3.2

Way Locking...................................................................................................... 2-20

2.5

Exception Model............................................................................................................ 2-21

2.5.1

PowerPC Exception Model........................................................................................ 2-21

2.5.2

Implementation-Specific Exception Model ............................................................... 2-22

2.6

Memory Management.................................................................................................... 2-25

2.6.1

PowerPC Memory Management................................................................................ 2-25

2.6.2

Implementation-Specific MMU Features .................................................................. 2-25

2.7

Instruction Timing.......................................................................................................... 2-26

2.8

Differences Between the MPC8280 G2_LE

Embedded Core and the MPC603e............................................................................ 2-27

Chapter 3

Memory Map

3.1

Internal Memory Map ...................................................................................................... 3-2

Part II

Configuration and Reset

Chapter 4

System Interface Unit (SIU)

4.1

System Configuration and Protection .............................................................................. 4-2

4.1.1

Bus Monitor ................................................................................................................. 4-3

4.1.2

Timers Clock................................................................................................................ 4-3

4.1.3

Time Counter (TMCNT).............................................................................................. 4-4

4.1.4

Periodic Interrupt Timer (PIT)..................................................................................... 4-5

4.1.5

Software Watchdog Timer ........................................................................................... 4-6

4.2

Interrupt Controller .......................................................................................................... 4-7

4.2.1

Interrupt Configuration ................................................................................................ 4-8

4.2.1.1

Machine Check Interrupt ......................................................................................... 4-9

4.2.1.2

INT Interrupt............................................................................................................4-9

4.2.2

Interrupt Source Priorities............................................................................................ 4-9

4.2.2.1

SCC, FCC, and MCC Relative Priority ................................................................. 4-12

4.2.2.2

PIT, TMCNT, PCI, and IRQ Relative Priority ...................................................... 4-13

4.2.2.3

Highest Priority Interrupt....................................................................................... 4-13

4.2.3

Masking Interrupt Sources......................................................................................... 4-13

4.2.4

Interrupt Vector Generation and Calculation ............................................................. 4-14

4.2.4.1

Port C External Interrupts ...................................................................................... 4-16

4.3

Programming Model ...................................................................................................... 4-17

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