MPC8280 datasheet(14/1386 Pages) FREESCALE

14 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

xiv

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

8.7.2

TLBISYNC Input ...................................................................................................... 8-31

8.8

Little-Endian Mode........................................................................................................ 8-31

Chapter 9

PCI Bridge

9.1

Signals.............................................................................................................................. 9-3

9.2

Clocking........................................................................................................................... 9-3

9.3

PCI Bridge Initialization .................................................................................................. 9-3

9.4

SDMA Interface...............................................................................................................9-3

9.5

Interrupts from PCI Bridge .............................................................................................. 9-4

9.6

60x Bus Arbitration Priority ............................................................................................ 9-4

9.7

60x Bus Masters............................................................................................................... 9-4

9.8

CompactPCI Hot Swap Specification Support ................................................................ 9-5

9.9

PCI Interface .................................................................................................................... 9-5

9.9.1

PCI Interface Operation ............................................................................................... 9-6

9.9.1.1

Bus Commands ........................................................................................................ 9-6

9.9.1.2

PCI Protocol Fundamentals ..................................................................................... 9-7

9.9.1.2.1

Basic Transfer Control......................................................................................... 9-8

9.9.1.2.2

Addressing ........................................................................................................... 9-8

9.9.1.2.3

Byte Enable Signals............................................................................................. 9-9

9.9.1.2.4

Bus Driving and Turnaround ............................................................................... 9-9

9.9.1.3

Bus Transactions...................................................................................................... 9-9

9.9.1.3.1

Read and Write Transactions ............................................................................... 9-9

9.9.1.3.2

Transaction Termination .................................................................................... 9-11

9.9.1.4

Other Bus Operations ............................................................................................ 9-13

9.9.1.4.1

Device Selection ................................................................................................ 9-13

9.9.1.4.2

Fast Back-to-Back Transactions ........................................................................ 9-14

9.9.1.4.3

Data Streaming .................................................................................................. 9-14

9.9.1.4.4

Host Mode Configuration Access...................................................................... 9-15

9.9.1.4.5

Agent Mode Configuration Access ................................................................... 9-16

9.9.1.4.6

Special Cycle Command ................................................................................... 9-16

9.9.1.4.7

Interrupt Acknowledge ...................................................................................... 9-17

9.9.1.5

Error Functions ...................................................................................................... 9-17

9.9.1.5.1

Parity.................................................................................................................. 9-17

9.9.1.5.2

Error Reporting.................................................................................................. 9-18

9.9.2

PCI Bus Arbitration ................................................................................................... 9-19

9.9.2.1

Bus Parking............................................................................................................ 9-19

9.9.2.2

Arbitration Algorithm............................................................................................ 9-19

9.9.2.3

Master Latency Timer............................................................................................ 9-20

9.10

Address Map .................................................................................................................. 9-21

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