MPC8280 datasheet(19/1386 Pages) FREESCALE

19 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

xix

Contents

Paragraph

Number

Title

Page

Number

11.3.4

Local Bus SDRAM Mode Register (LSDMR)........................................................ 11-24

11.3.5

Machine A/B/C Mode Registers (MxMR)............................................................... 11-26

11.3.6

Memory Data Register (MDR) ................................................................................ 11-28

11.3.7

Memory Address Register (MAR) .......................................................................... 11-29

11.3.8

60x Bus-Assigned UPM Refresh Timer (PURT)..................................................... 11-30

11.3.9

Local Bus-Assigned UPM Refresh Timer (LURT) ................................................. 11-30

11.3.10

60x Bus-Assigned SDRAM Refresh Timer (PSRT)................................................ 11-31

11.3.11

Local Bus-Assigned SDRAM Refresh Timer (LSRT) ............................................ 11-32

11.3.12

Memory Refresh Timer Prescaler Register (MPTPR) ............................................. 11-32

11.3.13

60x Bus Error Status and Control Registers (TESCRx) .......................................... 11-33

11.3.14

Local Bus Error Status and Control Registers (L_TESCRx) .................................. 11-33

11.4

SDRAM Machine ........................................................................................................ 11-33

11.4.1

Supported SDRAM Configurations......................................................................... 11-35

11.4.2

SDRAM Power-On Initialization ............................................................................ 11-35

11.4.3

JEDEC-Standard SDRAM Interface Commands .................................................... 11-35

11.4.4

Page-Mode Support and Pipeline Accesses............................................................. 11-36

11.4.5

Bank Interleaving .................................................................................................... 11-36

11.4.5.1

Using BNKSEL Signals in Single-MPC8280 Bus Mode.................................... 11-37

11.4.5.2

SDRAM Address Multiplexing (SDAM and BSMA)......................................... 11-37

11.4.6

SDRAM Device-Specific Parameters...................................................................... 11-38

11.4.6.1

Precharge-to-Activate Interval............................................................................. 11-39

11.4.6.2

Activate to Read/Write Interval ........................................................................... 11-39

11.4.6.3

Column Address to First Data Out—CAS Latency............................................. 11-40

11.4.6.4

Last Data Out to Precharge.................................................................................. 11-41

11.4.6.5

Last Data In to Precharge—Write Recovery ....................................................... 11-41

11.4.6.6

Refresh Recovery Interval (RFRC) ..................................................................... 11-42

11.4.6.7

External Address Multiplexing Signal................................................................. 11-42

11.4.6.8

External Address and Command Buffers (BUFCMD)........................................ 11-42

11.4.7

SDRAM Interface Timing ....................................................................................... 11-43

11.4.8

SDRAM Read/Write Transactions........................................................................... 11-46

11.4.9

SDRAM Mode-Set Command Timing .................................................................... 11-47

11.4.10

SDRAM Refresh...................................................................................................... 11-47

11.4.11

SDRAM Refresh Timing ......................................................................................... 11-48

11.4.12

SDRAM Configuration Examples ........................................................................... 11-48

11.4.12.1

SDRAM Configuration Example (Page-Based Interleaving).............................. 11-49

11.4.13

SDRAM Configuration Example (Bank-Based Interleaving) ................................. 11-50

11.5

General-Purpose Chip-Select Machine (GPCM)......................................................... 11-52

11.5.1

Timing Configuration .............................................................................................. 11-53

11.5.1.1

Chip-Select Assertion Timing ............................................................................. 11-54

11.5.1.2

Chip-Select and Write Enable Deassertion Timing ............................................. 11-55

11.5.1.3

Relaxed Timing.................................................................................................... 11-56

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