MPC8280 datasheet(20/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

11.5.1.4

Output Enable (OE) Timing ................................................................................ 11-58

11.5.1.5

Programmable Wait State Configuration ............................................................. 11-59

11.5.1.6

Extended Hold Time on Read Accesses .............................................................. 11-59

11.5.2

External Access Termination ................................................................................... 11-61

11.5.3

Boot Chip-Select Operation..................................................................................... 11-62

11.5.4

Differences Between the MPC8xx GPCM and MPC82xx GPCM .......................... 11-63

11.6

User-Programmable Machines (UPMs)....................................................................... 11-63

11.6.1

Requests ................................................................................................................... 11-65

11.6.1.1

Memory Access Requests.................................................................................... 11-66

11.6.1.2

UPM Refresh Timer Requests ............................................................................. 11-66

11.6.1.3

Software Requests—run Command .................................................................... 11-67

11.6.1.4

Exception Requests.............................................................................................. 11-67

11.6.2

Programming the UPMs .......................................................................................... 11-67

11.6.3

Clock Timing ........................................................................................................... 11-68

11.6.4

The RAM Array....................................................................................................... 11-70

11.6.4.1

RAM Words ......................................................................................................... 11-71

11.6.4.1.1

Chip-Select Signals (CxTx) ............................................................................. 11-75

11.6.4.1.2

Byte-Select Signals (BxTx) ............................................................................. 11-76

11.6.4.1.3

General-Purpose Signals (GxTx, GOx) ........................................................... 11-77

11.6.4.1.4

Loop Control.................................................................................................... 11-77

11.6.4.1.5

Repeat Execution of Current RAM Word (REDO) ........................................ 11-77

11.6.4.2

Address Multiplexing .......................................................................................... 11-78

11.6.4.3

Data Valid and Data Sample Control................................................................... 11-78

11.6.4.4

Signals Negation.................................................................................................. 11-79

11.6.4.5

The Wait Mechanism ........................................................................................... 11-79

11.6.4.6

Extended Hold Time on Read Accesses ............................................................. 11-80

11.6.5

UPM DRAM Configuration Example ..................................................................... 11-80

11.6.6

Differences Between the MPC8xx UPM and MPC82xx UPM ............................... 11-81

11.7

Memory System Interface Example Using UPM ........................................................ 11-82

11.7.0.1

EDO Interface Example....................................................................................... 11-93

11.8

Handling Devices with Slow or Variable Access Times............................................ 11-101

11.8.1

Hierarchical Bus Interface Example ...................................................................... 11-101

11.8.2

Slow Devices Example .......................................................................................... 11-101

11.9

External Master Support (60x-Compatible Mode) .................................................... 11-101

11.9.1

60x-Compatible External Masters (non-MPC8280).............................................. 11-102

11.9.2

MPC8280 External Masters................................................................................... 11-102

11.9.3

Extended Controls in 60x-Compatible Mode ........................................................ 11-102

11.9.4

Address Incrementing for External Bursting Masters ........................................... 11-102

11.9.5

External Masters Timing........................................................................................ 11-103

11.9.5.1

Example of External Master Using the SDRAM Machine ............................... 11-105

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