MPC8280 datasheet(97/1386 Pages) FREESCALE

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Overview

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

1-3

— 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port

— Uses the local bus signals, removing need for additional pins

•

System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

•

12-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-

definable peripherals

— Byte write enables and selectable parity generation

— 32-bit address decodes with programmable bank size

— Three user-programmable machines, general-purpose chip-select machine, and page-mode

pipeline SDRAM machine

— Byte selects for 64-bit bus width (60x) and for 32-bit bus width (local)

— Dedicated interface logic for SDRAM

•

CPU core can be disabled and the device can be used in slave mode to an external core

•

Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support

for communications protocols

— Interfaces to G2_LE core through an on-chip 32-Kbyte dual-port data RAM, an on-chip

32-Kbyte dual-port instruction RAM and DMA controller

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Three fast communications controllers supporting the following protocols:

– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent

interface (MII) or reduced media independent interface (RMII)

– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,

AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external

connections (no ATM support for the MPC8270)

– Transparent

– HDLC—Up to T3 rates (clear channel)

– FCC2 can also be connected to the TC layer (MPC8280 only)

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