MPC8280 datasheet(12/1386 Pages) FREESCALE

12 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

xii

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

7.2.3.1.1

Address Bus (A[0–31])—Output......................................................................... 7-6

7.2.3.1.2

Address Bus (A[0–31])—Input ........................................................................... 7-7

7.2.4

Address Transfer Attribute Signals.............................................................................. 7-7

7.2.4.1

Transfer Type (TT[0–4]).......................................................................................... 7-7

7.2.4.1.1

Transfer Type (TT[0–4])—Output....................................................................... 7-7

7.2.4.1.2

Transfer Type (TT[0–4])—Input ......................................................................... 7-7

7.2.4.2

Transfer Size (TSIZ[0–3]) ....................................................................................... 7-7

7.2.4.3

Transfer Burst (TBST)............................................................................................. 7-8

7.2.4.4

Global (GBL)........................................................................................................... 7-8

7.2.4.4.1

Global (GBL)—Output........................................................................................ 7-8

7.2.4.4.2

Global (GBL)—Input .......................................................................................... 7-8

7.2.4.5

Caching-Inhibited (CI)—Output ............................................................................. 7-9

7.2.4.6

Write-Through (WT)—Output ................................................................................ 7-9

7.2.5

Address Transfer Termination Signals......................................................................... 7-9

7.2.5.1

Address Acknowledge (AACK) .............................................................................. 7-9

7.2.5.1.1

Address Acknowledge (AACK)—Output........................................................... 7-9

7.2.5.1.2

Address Acknowledge (AACK)—Input ........................................................... 7-10

7.2.5.2

Address Retry (ARTRY)........................................................................................ 7-10

7.2.5.2.1

Address Retry (ARTRY)—Output .................................................................... 7-10

7.2.5.2.2

Address Retry (ARTRY)—Input ....................................................................... 7-10

7.2.6

Data Bus Arbitration Signals ..................................................................................... 7-11

7.2.6.1

Data Bus Grant (DBG) .......................................................................................... 7-11

7.2.6.1.1

Data Bus Grant (DBG)—Input.......................................................................... 7-11

7.2.6.1.2

Data Bus Grant (DBG)—Output ....................................................................... 7-11

7.2.6.2

Data Bus Busy (DBB) ........................................................................................... 7-12

7.2.6.2.1

Data Bus Busy (DBB)—Output ........................................................................ 7-12

7.2.6.2.2

Data Bus Busy (DBB)—Input ........................................................................... 7-12

7.2.7

Data Transfer Signals................................................................................................. 7-12

7.2.7.1

Data Bus (D[0–63]) ............................................................................................... 7-13

7.2.7.1.1

Data Bus (D[0–63])—Output ............................................................................ 7-13

7.2.7.1.2

Data Bus (D[0–63])—Input............................................................................... 7-13

7.2.7.2

Data Bus Parity (DP[0–7])..................................................................................... 7-13

7.2.7.2.1

Data Bus Parity (DP[0–7])—Output ................................................................. 7-14

7.2.7.2.2

Data Bus Parity (DP[0–7])—Input .................................................................... 7-14

7.2.8

Data Transfer Termination Signals ............................................................................ 7-14

7.2.8.1

Transfer Acknowledge (TA) .................................................................................. 7-14

7.2.8.1.1

Transfer Acknowledge (TA)—Input ................................................................. 7-15

7.2.8.1.2

Transfer Acknowledge (TA)—Output............................................................... 7-15

7.2.8.2

Transfer Error Acknowledge (TEA)...................................................................... 7-16

7.2.8.2.1

Transfer Error Acknowledge (TEA)—Input ..................................................... 7-16

7.2.8.2.2

Transfer Error Acknowledge (TEA)—Output................................................... 7-16

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