MPC8280 datasheet(13/1386 Pages) FREESCALE

13 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

xiii

Contents

Paragraph

Number

Title

Page

Number

7.2.8.3

Partial Data Valid Indication (PSDVAL) ............................................................... 7-16

7.2.8.3.1

Partial Data Valid (PSDVAL)—Input................................................................ 7-17

7.2.8.3.2

Partial Data Valid (PSDVAL)—Output ............................................................. 7-17

Chapter 8

The 60x Bus

8.1

Terminology ..................................................................................................................... 8-1

8.2

Bus Configuration............................................................................................................8-2

8.2.1

Single-MPC8280 Bus Mode........................................................................................ 8-2

8.2.2

60x-Compatible Bus Mode.......................................................................................... 8-3

8.3

60x Bus Protocol Overview ............................................................................................. 8-4

8.3.1

Arbitration Phase ......................................................................................................... 8-5

8.3.2

Address Pipelining and Split-Bus Transactions........................................................... 8-6

8.4

Address Tenure Operations.............................................................................................. 8-7

8.4.1

Address Arbitration...................................................................................................... 8-7

8.4.2

Address Pipelining....................................................................................................... 8-8

8.4.3

Address Transfer Attribute Signals.............................................................................. 8-9

8.4.3.1

Transfer Type Signal (TT[0–4]) Encoding .............................................................. 8-9

8.4.3.2

Transfer Code Signals TC[0–2] ............................................................................. 8-12

8.4.3.3

TBST and TSIZ[0–3] Signals and Size of Transfer .............................................. 8-12

8.4.3.4

Burst Ordering During Data Transfers .................................................................. 8-13

8.4.3.5

Effect of Alignment on Data Transfers.................................................................. 8-14

8.4.3.6

Effect of Port Size on Data Transfers .................................................................... 8-15

8.4.3.7

60x-Compatible Bus Mode—Size Calculation ..................................................... 8-17

8.4.3.8

Extended Transfer Mode ....................................................................................... 8-18

8.4.4

Address Transfer Termination ................................................................................... 8-21

8.4.4.1

Address Retried with ARTRY ............................................................................... 8-21

8.4.4.2

Address Tenure Timing Configuration .................................................................. 8-23

8.4.5

Pipeline Control ......................................................................................................... 8-23

8.5

Data Tenure Operations ................................................................................................. 8-24

8.5.1

Data Bus Arbitration.................................................................................................. 8-24

8.5.2

Data Streaming Mode ................................................................................................ 8-25

8.5.3

Data Bus Transfers and Normal Termination ............................................................ 8-25

8.5.4

Effect of ARTRY Assertion on Data Transfer and Arbitration ................................. 8-26

8.5.5

Port Size Data Bus Transfers and PSDVAL Termination.......................................... 8-26

8.5.6

Data Bus Termination by Assertion of TEA.............................................................. 8-28

8.6

Memory Coherency—MEI Protocol ............................................................................. 8-29

8.7

Processor State Signals .................................................................................................. 8-30

8.7.1

Support for the lwarx/stwcx. Instruction Pair ........................................................... 8-31

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