MPC8280 datasheet(8/1386 Pages) FREESCALE

8 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

viii

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

1.7.2.2

High-Performance Communication....................................................................... 1-18

1.7.2.3

High-Performance System Microprocessor........................................................... 1-19

1.7.2.4

PCI ......................................................................................................................... 1-20

1.7.2.5

PCI with 155-Mbps ATM ...................................................................................... 1-20

1.7.2.6

The MPC8280 as PCI Agent ................................................................................. 1-21

Chapter 2

G2_LE Core

2.1

Overview.......................................................................................................................... 2-1

2.2

G2_LE Core Features ..................................................................................................... 2-3

2.2.1

Instruction Unit ............................................................................................................ 2-5

2.2.2

Instruction Queue and Dispatch Unit........................................................................... 2-5

2.2.3

Branch Processing Unit (BPU) .................................................................................... 2-6

2.2.4

Independent Execution Units....................................................................................... 2-6

2.2.4.1

Integer Unit (IU) ...................................................................................................... 2-6

2.2.4.2

Floating-Point Unit (FPU) ....................................................................................... 2-6

2.2.4.3

Load/Store Unit (LSU) ............................................................................................ 2-7

2.2.4.4

System Register Unit (SRU).................................................................................... 2-7

2.2.5

Completion Unit .......................................................................................................... 2-7

2.2.6

Memory Subsystem Support........................................................................................ 2-7

2.2.6.1

Memory Management Units (MMUs)..................................................................... 2-8

2.2.6.2

Cache Units..............................................................................................................2-8

2.3

Programming Model ........................................................................................................ 2-8

2.3.1

Register Set .................................................................................................................. 2-8

2.3.1.1

PowerPC Register Set.............................................................................................. 2-9

2.3.1.2

MPC8280-Specific Registers................................................................................. 2-11

2.3.1.2.1

Hardware Implementation-Dependent Register 0 (HID0) ................................ 2-11

2.3.1.2.2

Hardware Implementation-Dependent Register 1 (HID1) ................................ 2-14

2.3.1.2.3

Hardware Implementation-Dependent Register 2 (HID2) ................................ 2-14

2.3.1.2.4

Processor Version Register (PVR)..................................................................... 2-15

2.3.2

PowerPC Instruction Set and Addressing Modes ...................................................... 2-15

2.3.2.1

Calculating Effective Addresses ............................................................................ 2-15

2.3.2.2

PowerPC Instruction Set........................................................................................ 2-16

2.3.2.3

MPC8280 Implementation-Specific Instruction Set.............................................. 2-17

2.4

Cache Implementation ................................................................................................... 2-18

2.4.1

PowerPC Cache Model.............................................................................................. 2-18

2.4.2

MPC8280 Implementation-Specific Cache Implementation ..................................... 2-18

2.4.2.1

Data Cache............................................................................................................. 2-19

2.4.2.2

Instruction Cache ................................................................................................... 2-20

2.4.2.3

Cache Locking ....................................................................................................... 2-20

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