MPC8280 datasheet(64/1386 Pages) FREESCALE

64 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxiv

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

33-19

Switch Receive/Transmit Buffer Descriptor ....................................................................... 33-29

33-20

SSSAR Rx Queue Descriptor ............................................................................................. 33-31

33-21

SSSAR Receive Buffer Descriptor ..................................................................................... 33-32

33-22

UDC Header Table .............................................................................................................. 33-37

33-23

AAL2 Interrupt Queue Entry CID

≠ 0 ................................................................................ 33-38

33-24

AAL2 Interrupt Queue Entry CID = 0 ................................................................................ 33-39

34-1

Basic Concept of IMA .......................................................................................................... 34-5

34-2

Illustration of IMA Frames ................................................................................................... 34-6

34-3

IMA Microcode Overview.................................................................................................... 34-7

34-4

IMA Frame and ICP Cell Formats ........................................................................................ 34-8

34-5

IMA Transmit Task Interaction........................................................................................... 34-10

34-6

Transmit Queue Normal Operating State............................................................................ 34-12

34-7

Transmit Queue Behavior: Link Clock Rate Same as TRL ................................................ 34-12

34-8

Transmit Queue Behavior: Link Clock Rate Slower than TRL .......................................... 34-13

34-9

Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case Event Sequence ......

34-14

34-10

IMA Receive Task Interaction ............................................................................................ 34-15

34-11

IMA Microcode: Receive Process ...................................................................................... 34-17

34-12

IMA Root Table Data Structures......................................................................................... 34-21

34-13

IMA Control (IMACNTL).................................................................................................. 34-25

34-14

IMA Group Transmit Control (IGTCNTL)......................................................................... 34-27

34-15

IMA Group Transmit State (IGTSTATE)............................................................................ 34-27

34-16

Transmit Group Order Table Entry ..................................................................................... 34-28

34-17

IMA Group Receive Control (IGRCNTL).......................................................................... 34-34

34-18

IMA Group Receive State (IGRSTATE)............................................................................. 34-34

34-19

IMA Receive Group Frame Size (IGRSTATE) .................................................................. 34-35

34-20

Receive Group Order Table Entry....................................................................................... 34-36

34-21

IMA Link Transmit Control (ILTCNTL)............................................................................ 34-38

34-22

IMA Link Transmit State (ILTSTATE) ............................................................................... 34-38

34-23

IMA Transmit Interrupt Status (ITINTSTAT)..................................................................... 34-39

34-24

IMA Link Receive Control (ILRCNTL)............................................................................. 34-41

34-25

IMA Link Receive State (ILRSTATE)................................................................................ 34-42

34-26

IMA Transmit Queue .......................................................................................................... 34-44

34-27

Cell Buffer in Delay Compensation Buffer......................................................................... 34-44

34-28

IMA Delay Compensation Buffer ....................................................................................... 34-45

34-29

IMA Interrupt Queue Entry................................................................................................. 34-45

34-30

IDMA Event/Mask Registers in IDCR Mode (IDSR/IDMR) ............................................ 34-50

34-31

COMM_INFO Field ........................................................................................................... 34-53

34-32

IMA Microcode/Software Interaction................................................................................. 34-54

34-33

Near-End versus Far-End .................................................................................................... 34-60

35-1

Serial ATM Using FCC2 and TC Blocks (Single Channel).................................................. 35-1

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