MPC8280 datasheet(49/1386 Pages) FREESCALE

49 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

xlix

Figures

Figure

Number

Title

Page

Number

Figures

1-1

MPC8280 Block Diagram....................................................................................................... 1-6

1-2

MPC8280 External Signals .....................................................................................................1-9

1-3

Remote Access Server Configuration ................................................................................... 1-13

1-4

Regional Office Router Configuration.................................................................................. 1-14

1-5

LAN-to-WAN Bridge Router Configuration ........................................................................ 1-15

1-6

Cellular Base Station Configuration ..................................................................................... 1-15

1-7

Telecommunications Switch Controller Configuration ........................................................ 1-16

1-8

SONET Transmission Controller Configuration .................................................................. 1-17

1-9

Basic System Configuration.................................................................................................. 1-18

1-10

High-Performance Communication ...................................................................................... 1-18

1-11

High-Performance System Microprocessor Configuration................................................... 1-19

1-12

PCI Configuration ................................................................................................................. 1-20

1-13

PCI with 155-Mbps ATM Configuration .............................................................................. 1-20

1-14

MPC8280 as PCI Agent ........................................................................................................1-21

2-1

MPC8280 Integrated Processor Core Block Diagram ............................................................ 2-2

2-2

MPC8280 Programming Model—Registers ......................................................................... 2-10

2-3

Hardware Implementation Register 0 (HID0) ...................................................................... 2-11

2-4

Hardware Implementation-Dependent Register 1 (HID1).................................................... 2-14

2-5

Hardware Implementation-Dependent Register 2 (HID2).................................................... 2-14

2-6

Data Cache Organization ......................................................................................................2-19

3-1

Internal Memory ..................................................................................................................... 3-1

4-1

SIU Block Diagram................................................................................................................. 4-1

4-2

System Configuration and Protection Logic ........................................................................... 4-3

4-3

Timers Clock Generation ........................................................................................................ 4-4

4-4

TMCNT Block Diagram ......................................................................................................... 4-5

4-5

PIT Block Diagram ................................................................................................................. 4-5

4-6

Software Watchdog Timer Service State Diagram.................................................................. 4-6

4-7

Software Watchdog Timer Block Diagram ............................................................................. 4-7

4-8

MPC8280 Interrupt Structure..................................................................................................4-8

4-9

Interrupt Request Masking....................................................................................................4-14

4-10

SIU Interrupt Configuration Register (SICR) ....................................................................... 4-17

4-11

SIU Interrupt Priority Register (SIPRR) ............................................................................... 4-18

4-12

CPM High Interrupt Priority Register (SCPRR_H).............................................................. 4-19

4-13

CPM Low Interrupt Priority Register (SCPRR_L)............................................................... 4-20

4-14

SIPNR_H .............................................................................................................................. 4-21

4-15

SIPNR_L ............................................................................................................................... 4-22

4-16

SIMR_H ................................................................................................................................ 4-23

4-17

SIMR_L ................................................................................................................................ 4-23

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