MPC8280 datasheet(16/1386 Pages) FREESCALE

16 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

xvi

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

9.11.2.16

Subsystem Device ID Register ............................................................................. 9-56

9.11.2.17

PCI Bus Capabilities Pointer Register .................................................................. 9-56

9.11.2.18

PCI Bus Interrupt Line Register ........................................................................... 9-57

9.11.2.19

PCI Bus Interrupt Pin Register ............................................................................. 9-57

9.11.2.20

PCI Bus MIN GNT ............................................................................................... 9-58

9.11.2.21

PCI Bus MAX LAT .............................................................................................. 9-58

9.11.2.22

PCI Bus Function Register ................................................................................... 9-59

9.11.2.23

PCI Bus Arbiter Configuration Register ............................................................... 9-60

9.11.2.24

PCI Hot Swap Register Block .............................................................................. 9-61

9.11.2.25

PCI Hot Swap Control Status Register ................................................................. 9-61

9.11.2.26

PCI Configuration Register Access from the Core ............................................... 9-62

9.11.2.27

PCI Configuration Register Access in Big-Endian Mode .................................... 9-62

9.11.2.27.1

Additional Information on Endianess ............................................................... 9-63

9.11.2.27.2

Notes on GPCR[LE_MODE] ........................................................................... 9-63

9.11.2.28

Initializing the PCI Configuration Registers ........................................................ 9-64

9.12

Message Unit (I2O) ....................................................................................................... 9-66

9.12.1

Message Registers...................................................................................................... 9-66

9.12.1.1

Inbound Message Registers (IMRx) ..................................................................... 9-67

9.12.1.2

Outbound Message Registers (OMRx) ................................................................. 9-67

9.12.2

Door Bell Registers ................................................................................................... 9-68

9.12.2.1

Outbound Doorbell Register (ODR) ..................................................................... 9-68

9.12.2.2

Inbound Doorbell Register (IDR) ......................................................................... 9-69

9.12.3

I2O Unit .................................................................................................................... 9-70

9.12.3.1

PCI Configuration Identification .......................................................................... 9-71

9.12.3.2

Inbound FIFOs ...................................................................................................... 9-71

9.12.3.2.1

Inbound Free_FIFO Head Pointer Register (IFHPR) and Inbound

Free_FIFO Tail Pointer Register (IFTPR) .................................................... 9-72

9.12.3.2.2

Inbound Post_FIFO Head Pointer Register (IPHPR) and Inbound

Post_FIFO Tail Pointer Register (IPTPR) .................................................... 9-73

9.12.3.3

Outbound FIFOs ................................................................................................... 9-75

9.12.3.3.1

Outbound Free_FIFO Head Pointer Register (OFHPR) and Outbound

Free_FIFO Tail Pointer Register (OFTPR) .................................................. 9-75

9.12.3.3.2

Outbound Post_FIFO Head Pointer Register (OPHPR) and Outbound

Post_FIFO Tail Pointer Register (OPTPR) ................................................... 9-76

9.12.3.4

I2O Registers.......................................................................................................... 9-78

9.12.3.4.1

Inbound FIFO Queue Port Register (IFQPR) ................................................... 9-78

9.12.3.4.2

Outbound FIFO Queue Port Register (OFQPR) ............................................... 9-79

9.12.3.4.3

Outbound Message Interrupt Status Register (OMISR) ................................... 9-80

9.12.3.4.4

Outbound Message Interrupt Mask Register (OMIMR) .................................. 9-81

9.12.3.4.5

Inbound Message Interrupt Status Register (IMISR) ....................................... 9-82

9.12.3.4.6

Inbound Message Interrupt Mask Register (IMIMR) ....................................... 9-83

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