MPC8280 datasheet(99/1386 Pages) FREESCALE

99 / 1386 page

Overview

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

1-5

– Transparent

– UART (low-speed operation)

— One serial peripheral interface identical to the MPC860 SPI

— One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller)

– Microwire compatible

– Multiple-master, single-master, and slave modes

— Up to eight TDM interfaces (four on the MPC8270)

– Supports two groups of four TDM channels for a total of eight TDMs (one group of four on

the MPC8270 and the MPC8275)

– 2,048 bytes of SI RAM

– Bit or byte resolution

– Independent transmit and receive routing, frame synchronization

– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN

primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and

user-defined TDM serial interfaces

— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,

SCCs, SMCs, and serial channels

— Four independent 16-bit timers that can be interconnected as two 32-bit timers

— Transmission convergence (TC) layer (MPC8280 only)

— Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only). Supported by eight TC

layers between the TDMs and FCC2.

1.2

Architecture Overview

The MPC8280 has two external buses to accommodate bandwidth requirements from the high-speed

system core and the very fast communications channels. Figure 1-1 shows the block diagram of the

superset MPC8280 device. Features that are device- or package-specific are noted. For package

information, refer to the MPC8280 PowerQUICC II Family Hardware Specifications (order number:

MPC8280EC).

MPC8280 数据表(PDF) 99 Page - Freescale Semiconductor, Inc