PIC16F753 datasheet(152/230 Pages) MICROCHIP

152 / 230 page

PIC16F753/HV753

DS40001709C-page 152

 2013-2015 Microchip Technology Inc.

TABLE 19-1:

TIME-OUT IN VARIOUS SITUATIONS

TABLE 19-2:

STATUS/PCON BITS AND THEIR SIGNIFICANCE

19.3.1

POWER-ON RESET (POR)

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operation. To take advantage of the POR, simply

connect the MCLR pin through a resistor to VDD. This

will eliminate external RC components usually needed

to create Power-on Reset. A maximum rise time for

VDD

required.

See

Section 22.0

“Electrical

Specifications” for details. If the BOR is enabled, the

maximum rise time specification does not apply. The

BOR circuitry will keep the device in Reset until VDD

reaches VBOR (see Section 19.3.4 “Brown-out Reset

(BOR)”).

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure proper operation. If these conditions are not

met, the device must be held in Reset until the

operating conditions are met.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

19.3.2

MCLR

PIC16F753/HV753 has a noise filter in the MCLR

Reset path. The filter will detect and ignore small

pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

Voltages applied to the MCLR pin that exceed its

specification can result in both MCLR Resets and

excessive current beyond the device specification

during the ESD event. For this reason, Microchip

recommends that the MCLR pin no longer be tied

directly to VDD. The use of an RC network, as shown in

Figure 19-2, is suggested.

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word register. When

MCLRE = 0, the Reset signal to the chip is generated

internally. When the MCLRE = 1, the MCLR pin

becomes an external Reset input. In this mode, the

MCLR pin has a weak pull-up to VDD.

FIGURE 19-2:

RECOMMENDED MCLR

CIRCUIT

Oscillator Configuration

Power-up

Brown-out Reset

Wake-up from

Sleep

PWRTE = 0

PWRTE = 1

PWRTE = 0

PWRTE = 1

EC, INTOSC

TPWRT

—TPWRT

——

POR

BOR

Condition

0x11

Power-on Reset

u011

Brown-out Reset

uu0u

WDT Reset

uu00

WDT Wake-up

uuuu

MCLR Reset during normal operation

uu10

MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

Note:

The POR circuit does not produce an

internal Reset when VDD declines. To re-

enable the POR, VDD must reach Vss for

a minimum of 100

s.

VDD

PIC®

MCLR

or greater)

0.1

F

(optional, not critical)

100



needed with capacitor)

SW1

(optional)

MCU

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