PIC16F753 datasheet(153/230 Pages) MICROCHIP

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DS40001709C-page 153

PIC16F753/HV753

19.3.3

POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 64 ms (nominal)

time-out on power-up only, from POR or Brown-out

Reset. The Power-up Timer operates from an internal

RC oscillator. For more information, see Section 4.2.2

“Internal Clock Mode”. The chip is kept in Reset as

long as PWRT is active. The PWRT delay allows the

VDD to rise to an acceptable level. A Configuration bit,

PWRTE, can disable (if set) or enable (if cleared or

programmed) the Power-up Timer. The Power-up

Timer should be enabled when Brown-out Reset is

enabled, although it is not required.

The Power-up Timer delay will vary from chip-to-chip

due to:

•VDD variation

• Temperature variation

• Process variation

See

parameters

for

details

(Section 22.0

“Electrical Specifications”).

19.3.4

BROWN-OUT RESET (BOR)

The BOREN<1:0> bits in the Configuration Word

has been added to allow control of the BOR enable for

lower current during Sleep. By selecting BOREN<1:0>

= 10, the BOR is automatically disabled in Sleep to

conserve power and enabled on wake-up. See

A brown-out occurs when VDD falls below VBOR for

greater than parameter TBOR (see Section 22.0

“Electrical Specifications”). The brown-out condition

will reset the device. This will occur regardless of VDD

slew rate. A Brown-out Reset may not occur if VDD falls

below VBOR for less than parameter TBOR.

On any Reset (Power-on, Brown-out Reset, Watchdog

timer, etc.), the chip will remain in Reset until VDD rises

above VBOR (see Figure 19-3). If enabled, the Power-

up Timer will be invoked by the Reset and keep the chip

in Reset an additional 64 ms.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

Table 19-3 summarizes the registers associated with

BOR.

FIGURE 19-3:

BROWN-OUT SITUATIONS

Note:

Voltage spikes below VSS at the MCLR

pin, inducing currents greater than 80 mA,

may cause latch-up. Thus, a series resis-

tor of 50-100  should be used when

applying a “low” level to the MCLR pin,

rather than pulling this pin directly to VSS.

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word

64 ms(1)

Vbor

VDD

Internal

Reset

Vbor

VDD

Internal

Reset

64 ms(1)

< 64 ms

64 ms(1)

Vbor

Vdd

Internal

Reset

Note 1:

64 ms delay only if PWRTE bit is programmed to ‘0’.

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