L9908 datasheet(107/152 Pages) STMICROELECTRONICS

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5.20.2

Frame description

The 32-bit SPI frames content is divided as follows:

Table 103. MOSI - SPI frame description

Bit

30-23

20-5

4-0

MOSI

R/W

ADDRESS

RSV/TM

DATA WRITE

CRC

MOSI Stream:

[31] R/W Flag. Selects if the current operation is a read (0) operation or write (1) operation.

[30-23] SPI register address

[22] Test Mode Flag

[21] Frame Counter

[20-5] Data Write

[4-0] CRC checksum generated by SPI-master

Table 104. MISO - SPI frame description

Bit

30-29

28-21

20-5

4-0

MISO

SPI ERR

IC ERR

ADDRESS FB

DATA READ

CRC

MISO Stream:

[31] SPI Error Flag. Provide information related to the previous stream.

[30-29] IC Error Flag. Provide information related to IC high level error.

[28-21] SPI register address feedback. Last received valid frame address feedback.

[20-5] Data Read. Data contents of SPI register addressed by last received valid frame.

[4-0] CRC checksum generated by SPI-slave

5.20.2.1

Write-Read operations

1st Frame: Write Access to R/W Register X

As the NCS rising edge is detected, if it is valid, the command is processed and the R/W register X is updated

with data Y. After the register X is updated correctly the output buffer is updated as well.

2nd Frame: Read Access

As the NCS falling edge is detected, the register X with data Y is started being shifted out on MISO bus. The X

data.

The first SPI frame after an internal reset (i.e. INT_RST) will have a fixed content:

•

IC_ERR and SPI_ERR flag all 0

•

Address Feedback all = 0

•

Data all = 0

L9908

Functional description

DS13546 - Rev 5

page 107/152

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