L9908 datasheet(110/152 Pages) STMICROELECTRONICS

110 / 152 page

5.20.3

Frame monitoring

Correct SPI communication is safety relevant and then the following safety mechanism is implemented.

Cyclic Redundancy Check (CRC)

MISO/MOSI SPI data are protected with a 5-bit CRC using the following polynomial expression:

Gx =x5+x2+1

(26)

The initial value to be used is 11111 (0x1F).

CRC is calculated over bit 5-31 except bit 21 (Hamming distance of 3 over 26 bit data), MSB First.

Example:

Read register 0x4A command (data = 0)

Frame: [0 0100:1010 0 0 0000:0000:0000:0000 10001] (0x25000011)

Frame: [0 0100:1010 0 1 0000:0000:0000:0000 10001] (0x25200011)

CRC is 10001 independently on FC value.

Write 0xABCD to register 0xC7 command

Frame: [1 1100:0111 0 0 1010:1011:1100:1101 11000] (0xE39579B8)

Frame: [1 1100:0111 0 1 1010:1011:1100:1101 11000] (0xE3B579B8)

CRC is 11000b independently on FC value.

Frame Counter Check (FC)

A 1-bit frame counter is transmitted by the SPI-master within every MOSI frame to support the detection of

failures in the communication channel (ex. corrupted or missing frames). The initial value to be used is 0.

Clock Counter Check

L9908 implements two separate clock counters for the rising and the falling edges of SCLK clock to check the

length of the MOSI frame to be equal to 32. The clock counters reset is generated from the detection of a rising

edge of NCS.

5.20.4

Error handling

In case of an error either regarding the SPI word length (clock counter), frame counter bit value (FC) or wrong

CRC check, the SPI_ERR bit is set to ‘1’ and the frame is ignored by L9908. The SPI error bit always refers to the

previous SPI frame.

The register SPI_CMM_FAULT contains specific bits indicating which SPI fault occurred on the previous frame.

After reading, register value will be reset. Refer to the next section for details.

5.20.5

Legenda:

Safety description:

•

NSR = Non-safety relevant Register

•

SLR = Safety latent Register

•

SSR = Safety relevant Register

Operation type:

•

RW = Read/Write

•

RO = Read only

•

CR = Clear on Read

Reset source:

•

A = INT_RST

•

B = INT_RST || CFG_RST

•

D = INT_RST (excluded CLK1_TIMEOUT)

Table 105. CHIPID

Address

Field name

Type

Bit offset

Bit width

Reset value

Reset

CHIPID

0x0

UNUSED_9

0x0

NSR

UNUSED_8

0x0

L9908

Functional description

DS13546 - Rev 5

page 110/152

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