 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADE75 数据表(PDF) 42 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADE75 数据表(HTML) 42 Page - Analog Devices |
|
|
42 / 148 page  ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 42 of 148 7 CF2 Logic one indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse output is not enabled by clearing bit 2 of MODE1 register. 6 CF1 Logic one indicates that a pulse on CF1 has been issued. The flag is set even if CF1 pulse output is not enabled by clearing bit 1 of MODE1 register. 5 VAEOF Logic one indicates that the VAHR register has overflowded 4 REOF11 Logic one indicates that the VARHR register has overflowded 3 AEOF Logic one indicates that the WATTHR register has overflowded 2 VAEHF Logic one indicates that the VAHR register is half full 1 REHF1 Logic one indicates that the VARHR register is half full 0 AEHF Logic one indicates that the WATTHR register is half full Table 38. Interrupt Status Register 3 SFR (MIRQSTH, 0xDE) Bit Location Interrupt Flag Description 7 RESET Indicates the end of a reset (for both sofware or hardware reset). 6 - Reserved 5 WFSM Logic one indicates that new data is present in the Waveform Registers 4 PKI Logic one indicates that current channel has exceeded the IPKLVL value 3 PKV Logic one indicates that voltage channel has exceeded the VPKLVL value. 2 CYCEND Logic one indicates the end of the energy accumulation over an integer number of half line cycles. 1 ZXTO Logic one indicates that no zero crossing on the line voltage happened for the last ZXTOUT half line cycles. 0 ZX Logic one indicates detection of a zero crossing in the voltage channel. Table 39. Interrupt Enable Register 1 SFR (MIRQENL, 0xD9) Bit Location Interrupt Flag Description 7-6 Reserved Reserved. 5 FAULTSIGN12 When this bit is set, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core. 4 VARSIGN1 When this bit is set, the VARSIGN bit set creates a pending ADE interrupt to the 8052 core. 3 APSIGN When this bit is set, the APSIGN bit set creates a pending ADE interrupt to the 8052 core. 2 VANOLOAD When this bit is set, the VANOLOAD bit set creates a pending ADE interrupt to the 8052 core. 1 RNOLOAD1 When this bit is set, the RNOLOAD bit set creates a pending ADE interrupt to the 8052 core. 0 APNOLOAD When this bit is set, the APNOLOAD bit set creates a pending ADE interrupt to the 8052 core. Table 40. Interrupt Enable Register 2 SFR (MIRQENM, 0xDA) Bit Location Interrupt Flag Description 7 CF2 When this bit is set, a CF2 pulse issued creates a pending ADE interrupt to the 8052 core. 6 CF1 When this bit is set, a CF1 pulse issued creates a pending ADE interrupt to the 8052 core. 5 VAEOF When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core. 4 REOF1 When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core. 3 AEOF When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core. 2 VAEHF When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core. 1 REHF1 When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core. 11 This function is not available in ADE7566 and ADE7166 products. 12 This function is not available in ADE7566 and ADE7569 products. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
