ADE75 datasheet(13/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 13 of 148

Table 4. SPI MASTER MODE TIMING (CPHA = 1) Parameter

Min

Typ

Max

Unit

tSL

SCLOCK Low Pulse Width1

977

tSH

SCLOCK High Pulse Width1

977

tDAV

Data Output Valid after SCLOCK Edge

TBD

tDSU

Data Input Setup Time before SCLOCK Edge

TBD

tDHD

Data Input Hold Time after SCLOCK Edge

TBD

tDF

Data Output Fall Time

tDR

Data Output Rise Time

tSR

SCLOCK Rise Time

tSF

SCLOCK Fall Time

____________________________________________

1 Characterized under the following conditions:

a. Core clock divider bits CD2, CD1, and CD0 in POWCON SFR set to 0, 0, and 0, respectively, that is, core clock frequency = 4.096/8 MHz.

b. SPI bit-rate selection bits SPIR1 and SPR0 in SPI2CMOD SFR set to 0 and 0, respectively.

SCLOCK

(CPOL = 0)

DSU

SCLOCK

(CPOL = 1)

MOSI

MISO

MSB

LSB

LSB IN

BITS 6–1

DHD

DAV

MSB IN

Figure 4. SPI Master Mode Timing (CPHA = 1)

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