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ADE75 数据表(PDF) 17 Page - Analog Devices |
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ADE75 数据表(HTML) 17 Page - Analog Devices |
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17 / 148 page ![]() Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 17 of 148 Table 8. UART Timing (Shift Register Mode) Parameter 4.09612.58 MHz Core_Clk Variable Core_Clk Min Typ Max Min Typ Max Unit TXLXL Serial Port Clock Cycle Time 2.93 12tcore μs TQVXH Output Data Setup to Clock TBD μs TDVXH Input Data Setup to Clock TBD μs TXHDX Input Data Hold after Clock TBD μs TXHQX Output Data Hold after Clock TBD μs SET RI OR SET TI BIT 6 tXLXL TxD (OUTPUT CLOCK) RxD (OUTPUT DATA) RxD (INPUT DATA) BIT 1 LSB LSB BIT 1 BIT 6 MSB tXHQX tQVXH tDVXH tXHDX Figure 8. UART Timing in Shift Register Mode SCLK CS t1 t10 t13 0 0 A4 A5 A3 A2 A1 A0 DB0 DB7 DB0 DB7 DIN DOUT t11 t11 t12 COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE t9 02875-0-083 |
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