ADE75 datasheet(61/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 61 of 148

Reactive Energy Calculation

As for active energy, the ADE75XX/ADE71XX achieves the

integration of the reactive power signal by continuously

accumulating the reactive power signal in an internal non-

readable 49-bit energy register. The reactive energy register

(VARHR[23:0]) represents the upper 24 bits of this internal

The discrete time sample period (T) for the accumulation

well as calculating the energy, this integration removes any

sinusoidal components that might be in the active power signal.

Figure 45 shows this discrete time integration or accumulation.

The reactive power signal in the waveform register is

continuously added to the internal reactive energy register.

The reactive Energy accumulation depends on the setting of the

SAVARM and ABSVARM bits in the ACCMODE register

(0x0F). When both bits are cleared, the addition is signed and

therefore negative energy is subtracted from the reactive energy

contents. When both bits are set, the ADE75XX/ADE71XX is

set to be in the more restrictive mode, the Absolute

Accumulation mode.

When SAVARM bit in the ACCMODE register (0x0F) is set,

the reactive power is accumulated depending on the sign of the

active power. When active power is positive, the reactive power

is added as it is to the reactive energy register. When active

power is negative, the reactive power is subtracted to the

reactive energy accumulator – see VAR anti-tamper

accumulation mode.

When ABSVARM bit in the ACCMODE register (0x0F) is set,

the absolute reactive power is used for the reactive energy

accumulation—see the VAR absolute accumulation mode

section.

The output of the multiplier is divided by VARDIV. If the value

in the VARDIV register is equal to 0, then the internal reactive

energy register is divided by 1. VARDIV is an 8-bit unsigned

accumulated in a 49-bit internal energy accumulation register.

The upper 24 bits of this register are accessible through a read

to the reactive energy register (VARHR[23:0]). A read to the

RVARHR register returns the content of the VARHR register

and the upper 24 bits of the internal register are cleared. As

shown in Figure 45, the reactive power signal is accumulated in

an internal 49-bit signed register. The reactive power signal can

be read from the waveform register by setting the WAVMODE

Enable Register 3 SFR (MIRQENH, 0xDB). Like the current and

voltage channels waveform sampling modes, the waveform date

is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or

3.5 kSPS.

Figure 40 shows this energy accumulation for full-scale signals

(sinusoidal) on the analog inputs. These curves also apply for

the reactive energy accumulation

Note that the energy register contents rolls over to full-scale

negative (0x800000) and continues to increase in value when

the power or energy flow is positive. Conversely, if the power is

negative, the energy register underflows to full-scale positive

(0x7FFFFF) and continues to decrease in value.

By using the interrupt enable register, the ADE75XX/ADE71XX

can be configured to issue an ADE interrupt to the 8052 core

when the reactive energy register is half-full (positive or

negative) or when an overflow or underflow occurs.

Integration time under steady Load

As mentioned in the active energy section, the discrete time

sample period (T) for the accumulation register is 1.22 μs

(5/CLKIN). With full-scale sinusoidal signals on the analog

inputs and the VARGAIN and VARDIV registers set to 0x000,

the integration time before the reactive energy register

overflows is calculated as follows:

Time =

xCCCCD

FFFF

FFFF,

xFFFF,

× 1.22 μs = 409.6 s = 6.82 min(15)

When VARDIV is set to a value different from 0, the integration

time varies, as shown in Equation 16.

VARDIV

Time

WDIV

= 0

(16)

Reactive energy accumulation modes

VAR signed accumulation mode

The ADE75XX/ADE71XX reactive energy default accumulation

mode is a signed accumulation based on the reactive power

information.

VAR anti-tamper accumulation mode

The ADE75XX/ADE71XX is placed in VAR anti-tamper

accumulation mode by setting the SAVARM bit in the

ACCMODE register (0x0F). In this mode, the reactive power is

accumulated depending on the sign of the active power. When

active power is positive, the reactive power is added as it is to

the reactive energy register. When active power is negative, the

reactive power is subtracted to the reactive energy accumulator

– see Figure 46. The CF pulse also reflects this accumulation

method when in this mode. The default setting for this mode is

off. Transitions in the direction of power flow, and no-load

threshold are active in this mode.

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