ADE75 datasheet(65/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 65 of 148

active and reactive energy register, these values can be

compared easily. The energies are calculated more accurately

because of this precise timing control and provide all the

information needed for reactive power and power factor

calculation. At the end of an energy calibration cycle, the

CYCEND flag in the Interrupt Status Register 3 SFR

(MIRQSTH, 0xDE) is set. If the CYCEND enable bit in the

Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is enabled,

the 8052 core has a pending ADE interrupt.

As for LWATTHR, when a new half line cycles is written in

LINECYC register, the LVAHR register is reset and a new

accumulation start at the next zero-crossing. The number of

half line cycles is then counted until LINCY is reached. This

implementation provides a valid measurement at the first

CYCEND interrupt after writing to the LINCYC register. The

line apparent energy accumulation uses the same signal path as

the apparent energy accumulation. The LSB size of these two

registers is equivalent.

VADIV[7:0]

LPF1

LVAHR [23:0]

LVAHR REGISTER IS

UPDATED EVERY LINCYC

ZERO CROSSINGS WITH THE

TOTAL APPARENT ENERGY

DURING THAT DURATION

APPARENT

POWER

FROM

VOLTAGE CHANNEL

ADC

LINCYC [15:0]

ZERO-CROSSING

DETECTION

CALIBRATION

CONTROL

Figure 51. ADE75XX/ADE71XX Line cycle Apparent Energy Accumulation

Apparent power no-Load detection

The ADE75XX/ADE71XX includes a no-load threshold feature

on the apparent energy that eliminates any creep effects in the

meter. The ADE75XX/ADE71XX accomplishes this by not

accumulating energy if the multiplier output is below the no-

load threshold. When the apparent power is below the no-load

threshold, the VANOLOAD flag in the Interrupt Status Register

1 SFR (MIRQSTL, 0xDC) is set. If the VANOLOAD bit is set in

the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the

8052 core has a pending ADE interrupt. The ADE interrupt

stays active until the APNOLOAD status bit is cleared—see

Energy measurement interrupts section.

The No-load threshold level is selectable by setting bits

VANOLOAD in the NLMODE register (0x0E). Setting these

bits to 0b00 disable the no-load detection and setting them to

0b01, 0b10 or 0b11 set the no-load detection threshold to

0.030%, 0.015% and 0.0075% of the full-scale output frequency

of the multiplier respectively.

This no-load threshold can also be applied to the Irms pulse

output when selected. The level of no-load threshold is the same

as for the Apparent energy in this case.

ENERGY-TO-FREQUENCY CONVERSION

ADE75XX/ADE71XX also provides two energy-to-frequency

conversions for calibration purposes. After initial calibration at

manufacturing, the manufacturer or end customer often verify

the energy meter calibration. One convenient way to verify the

meter calibration is for the manufacturer to provide an output

frequency, which is proportional to the active, reactive, apparent

power or Irms under steady load conditions. This output

frequency can provide a simple, single-wire, optically isolated

interface to external calibration equipment. Figure 52 illustrates

the energy-to-frequency conversion in the

ADE75XX/ADE71XX.

CFx

Pulse

output

CFxNUM

CFxDEN

DFC

VAR

Irms

CFxSEL[1:0]

WATT

VARMSCFCON

MODE2 Register 0x0C

Figure 52. ADE75XX/ADE71XX Energy-to-Frequency Conversion

Two digital-to-frequency converters (DFC) are used to generate

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