ADE75 datasheet(91/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 91 of 148

WATCHDOG TIMER

The watchdog timer generates a device reset or interrupt within a

reasonable amount of time if the ADE75XX/ADE71XX enters

an erroneous state, possibly due to a programming error or

electrical noise. The watchdog is enabled by default with a time

out of 2 seconds and will create a system reset if not cleared

within 2 seconds. The watchdog function can be disabled by

clearing the WDE (watchdog enable) bit in the watchdog

control (WatchDog Timer SFR (WDCON, 0xC0).

The watchdog circuit generates a system reset or interrupt

(WDS) if the user program fails to set the WDE bit within a

predetermined amount of time (see the PRE3…0 bits in

WatchDog Timer SFR (WDCON, 0xC0)). The watchdog timer

is clocked from the 32.768 kHz external crystal connected

between the CLKIN and CLKOUT pins. The WDCON SFR can

be written only by user software if the double write sequence

described in Table 71 is initiated on every write access to the

WDCON SFR.

In order to prevent any code from inadverdently disabling the

watchdog, a watchdog protection can be activated. This

watchdog protection locks in the watchdog enable and event

settings so that they cannot be changed by user code. The

protection is activated by clearing a watchdog protection bit in

the Flash memory. The watchdog protection bit is the most

significant bit at the address 0x3FFA of the Flash memory.

When this bit is cleared, the WDIR bit is forced to 0 and the

WDE bit is forced to 1. Note that the sequence for configuring

the flash protection bits must be followed to modify the

watchdog protection bit at 0x3FFA—see the Protecting the

Flash section.

Table 71. WatchDog Timer SFR (WDCON, 0xC0)

Bit

Location

Bit

Addr.

Bit

Name

Default

Value

Description

7-4

0xC7 –

0xC4

PRE[3:0]

Watchdog pre-scaler. In normal mode, the 16-bit watchdog timer is clocked by the

input clock (32.768kHz). The PRE bits set which of the upper bits of the counter are

used as the watchdog output following:

CLKIN

PRE

watchdog

[3:0]

Watchdog Timeout

0000

15.6ms

0001

31.2ms

0010

62.5ms

0011

125ms

0100

250ms

0101

500ms

0110

0111

1000

Automatic Reset

1001

Serial download reset

1010 to 1111

Not a valid selection

0xC3

WDIR

Watchdog interrupt response bit.

When clear, watchdog will generate a system reset when the watchdog time out

period has expired

When set, the watchdog will generate a interrupt when the watchdog time out

period has expired.

0xC2

WDS

WDS Watchdog status bit.

This bit is set to indicate that a watchdog timeout has occurred.

WDS is cleared by writing a zero or by an external hardware reset. A watchdog

reset will not clear WDS. The bit can therefore be used to distinguish between a

watchdog reset and a hardware reset from the RESET pin.

0xC1

WDE

WDE Watchdog enable bit.

When set, enables the watchdog and clears its counter (e.g. 2 above). The

watchdog counter is subsequently cleared again whenever the WDE bit is set. If

the watchdog is not cleared within its selected timeout period it will generate a

system reset or watchdog interrupt, depending on the WDIR bit.

0xC0

WDWR

WDWR Watchdog write enable bit. To write data into the WDCON SFR involves a

double instruction sequence. The WDWR bit must be set and the following

instruction must be a write instruction to the WDCON SFR. This sequence is

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