ADE75 datasheet(51/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 51 of 148

PKV bits are set in Interrupt Enable Register 3 SFR

(MIRQENH, 0xDB), the 8052 core has a pending ADE

interrupt.

Peak Level Record

The ADE75XX/ADE71XX records the maximum absolute value

reached by the voltage and current channels in two different

registers—IPEAK and VPEAK, respectively. VPEAK and IPEAK

are 16-bit unsigned registers. These registers are updated each

time the absolute value of the waveform sample from the

corresponding channel is above the value stored in the VPEAK

or IPEAK register. The contents of the VPEAK register

correspond to the maximum absolute value observed on the

voltage channel input. The contents of IPEAK and VPEAK

represent the maximum absolute value observed on the Current

and Voltage input respectively. Reading the RSTVPEAK and

RSTIPEAK registers clears their respective contents after the read

operation.

PHASE COMPENSATION

The ADE75XX/ADE71XX must work with transducers, which

could have inherent phase errors. For example, a phase error of

0.1° to 0.3° is not uncommon for a current transformer (CT).

These phase errors can vary from part to part, and they must be

corrected in order to perform accurate power calculations. The

errors associated with phase mismatch are particularly

noticeable at low power factors. The ADE75XX/ADE71XX

provides a means of digitally calibrating these small phase

errors. The ADE75XX/ADE71XX allows a small time delay or

time advance to be introduced into the signal processing chain

to compensate for small phase errors. Because the

compensation is in time, this technique should be used only for

small phase errors in the range of 0.1° to 0.5°. Correcting large

phase errors using a time shift technique can introduce

significant phase errors at higher harmonics.

The phase calibration register (PHCAL[7:0]) is a twos comple-

ment signed single-byte register that has values ranging from

0x82 (–126d) to 0x68 (104d).

The register is centered at 0x40, so that writing 0x40 to the

delay in the Voltage channel signal path can change from –

231.93 μs to +48.83 μs (MCLK = 4.096 MHz). One LSB is

equivalent to 1.22 μs (MCLK/5) time delay or advance. A line

frequency of 60 Hz gives a phase resolution of 0.026° at the

fundamental (i.e., 360° × 1.22 μs × 60 Hz)) or 0.00732% of the

line period. Similarly, a line frequency of 50Hz gives a phase

resolution of 0.022° at the fundamental or 0.0061% of the line

period. Figure 33 illustrates how the phase compensation is

used to remove a 0.1° phase lead in Current channel due to the

external transducer. To cancel the lead (0.1°) in Current

channel, a phase lead must also be introduced into Voltage

channel. The resolution of the phase adjustment allows the

introduction of a phase lead in increment of 0.026°. The phase

lead is achieved by introducing a time advance into Voltage

channel. A time advance of 4.88 μs is made by writing −4

(0x3C) to the time delay block, thus reducing the amount of

time delay by 4.88 μs, or equivalently, a phase lead of

approximately 0.1° at line frequency of 60 Hz. 0x3C represents –4

because the register is centered with 0 at 0x40.

PGA1

IPA

ADC 1

HPF

PGA2

ADC 2

DELAY BLOCK

1.22

μs/LSB

LPF2

60Hz

0.1°

CHANNEL 2 DELAY

REDUCED BY 4.48

μs

(0.1°LEAD AT 60Hz)

0Bh IN PHCAL [5.0]

PHCAL [7:0]

--231.93

μs TO +48.83μs

60Hz

Figure 33. Phase Calibration

ADE75XX/ADE71XX RMS CALCULATION

Root mean square (rms) value of a continuous signal V(t) is

defined as

VRMS =

∫

rms

)

(

(2)

For time sampling signals, rms calculation involves squaring the

signal, taking the average and obtaining the square root. The

ADE75XX/ADE71XX implements this method by serially

squaring the input, averaging them and then taking the root

square of the average. The averaging part of this signal

processing is done by implementing a Low Pass filter (LPF3 in

Figure 35 and Figure 36). This LPF has a -3dB cut-off frequency

of 2Hz when MCLK = 4.096MHz.

V(t) =

)

sin(

where: V is the rms voltage.

( )t

cos

)

(

−

When this signal goes through LPF3, the cos(2ωt) term is

attenuated and only the DC term Vrms2 goes through – see

Figure 34.

LPF3

INPUT

V(t)=

( )t

cos

)

(

−

)

(

)

sin(

ωω

⋅

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