ADE75 datasheet(43/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 43 of 148

AEHF

When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.

Table 41. Interrupt Enable Register 3 SFR (MIRQENH, 0xDB)

Bit

Location

Interrupt Flag

Description

7-6

Reserved

WFSM

When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core.

PKI

When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core.

PKV

When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core..

CYCEND

When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.

ZXTO

When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.

When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.

ANALOG INPUTS

The ADE75XX/ADE71XX has two fully differential voltage

input channels. The maximum differential input voltage for

input pairs VP/VN and IP/IN are ±0.5 V. In addition, the

maximum signal level on analog inputs for VP/VN and IP/ IN

is ±0.5 V with respect to AGND.

Each analog input channel has a PGA (programmable gain

amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The

gain selections are made by writing to the GAIN register in the

Energy Measurement Register List—see Table 34 and

RESERVED

GAIN REGISTER*

CURRENT AND VOLTAGE CHANNELS PGA CONTROL

ADDR:

1BH

* REGISTER CONTENTS

SHOW POWER-ON DEFAULTS

PGA 2 GAIN SELECT

000 = x 1

001 = x 2

010 = x 4

011 = x 8

100 = x 16

PGA 1 GAIN SELECT

000 = x 1

001 = x 2

010 = x 4

011 = x 8

100 = x 16

Figure 17. Bits 0 to 2 select the gain for the PGA in the current

channel, and the gain selection for the PGA in voltage channel is

made via Bits 5 to 7. Figure 16 shows how a gain selection for

the current channel is made using the gain register.

V1P

V1N

VIN

⋅ V

GAIN[7:0]

GAIN (K)

SELECTION

Figure 16. PGA in current channel

In addition to the PGA, Channel 1 also has a full-scale input range selection

for the ADC. The ADC analog input range selection is also made using the

gain register—see

RESERVED

GAIN REGISTER*

CURRENT AND VOLTAGE CHANNELS PGA CONTROL

ADDR:

1BH

* REGISTER CONTENTS

SHOW POWER-ON DEFAULTS

PGA 2 GAIN SELECT

000 = x 1

001 = x 2

010 = x 4

011 = x 8

100 = x 16

PGA 1 GAIN SELECT

000 = x 1

001 = x 2

010 = x 4

011 = x 8

100 = x 16

Figure 17. As mentioned previously, the maximum differential

input voltage is 0.5 V.

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