ADE75 datasheet(87/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 87 of 148

INTERRUPT PRIORITY

If two interrupts of the same priority level occur simultaneously, the polling sequence, as shown in

Table 67, is observed.

Table 67. Priority within Interrupt Level

Source

Priority

Description

IPSM

0 (Highest)

Power Supply Monitor Interrupt

IRTC

RTC interrupt

IADE

ADE Energy measurement interrupt

WDT

Watchdog Timer Overflow Interrupt

ITEMP

Temperature ADC interrupt

IE0

External Interrupt 0

TF0

Timer/Counter 0 Interrupt

IE1

External Interrupt 1

TF1

Timer/Counter 1 Interrupt

ISPI/I2CI

SPI/I2C Interrupt

RI/TI

UART Serial Port Interrupt

TF2/EXF2

11 (Lowest)

Timer/Counter 2 Interrupt

INTERRUPT FLAGS

The interrupt and status flags associated with the interrupt vectors are shown in Table 68 and Table 69. Most of the interrupts have flags

associated with them.

Table 68. Interrupt Flags

Interrupt Source

Flags

Bit

Address

Details

IE0

TCON.1

IE0

External Interrupt 0

Note: The INT0PRG bit must be set in the Interrupt pins configuration SFR

(INTPR, 0xFF) to allow the INT0 signal into the chip

TF0

TCON.5

TF0

Timer 0

IE1

TCON.3

IE1

External Interrupt 1

Note: The INT1PRG[2] bit must be set in the Interrupt pins configuration SFR

(INTPR, 0xFF) to allow the INT1 signal into the chip

TF1

TCON.7

TF1

Timer 1

SCON.1

Transmit Interrupt

RI + TI

SCON.0

Receive Interrupt

T2CON.7

TF2

Timer 2 overflow flag

TF2 + EXF2

T2CON.6

EXF2

Timer 2 external flag

ITEMP (Temperature

ADC)

The Temperature ADC interrupt does not have an interrupt flag associated with

it.

IPSM (Power Supply)

IPSMF.6

FPSM

PSM interrupt flag

IADE (Energy

Measurement DSP)

MIRQSTL.7

Read MIRQSTH, MIRQSTM, MIRQSTL. Write a “0” to a bit to clear and

acknowledge the event.

Table 69. Status Flags

Interrupt Source

Flags

Bit

Address

Details

ITEMP (Temperature ADC)

The Temperature ADC interrupt does not have an status flag associated with it.

ISPI/I2CI

SPISTAT

SPI Interrupt Status register

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