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M306V2EEFS 数据表(PDF) 101 Page - Renesas Technology Corp |
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M306V2EEFS 数据表(HTML) 101 Page - Renesas Technology Corp |
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101 / 271 page  Rev.1.40 Oct 06, 2004 page 101 of 269 M306V2ME-XXXFP, M306V2EEFP Figure 2.11.2 Block diagram of UART0 transmit/receive unit SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type TxD0 UART0 transmit register PAR enabled PAR disabled D8 D7 D6 D5 D4 D3 D2 D1 D0 SP: Stop bit PAR: Parity bit UART0 transmit buffer register MSB/LSB conversion circuit UART (8 bits) UART (9 bits) Clock synchronous type UART0 receive buffer register UARTi receive register 2SP 1SP PAR enabled PAR disabled UART UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type UART (7 bits) UART (8 bits) RxD0 Clock synchronous type UART (8 bits) UART (9 bits) Address 03A616 Address 03A716 Address 03A216 Address 03A316 Data bus low-order bits MSB/LSB conversion circuit D7 D6 D5 D4 D3 D2 D1 D0 D8 0000 000 SP SP PAR “0” Data bus high-order bits |
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