M306V2EEFS datasheet(104/271 Pages) RENESAS

104 / 271 page

Rev.1.40

Oct 06, 2004 page 104 of 269

M306V2ME-XXXFP, M306V2EEFP

UART2 transmit/receive mode register

Symbol

Address

When reset

U2MR

037816

0016

Bit name

Bit

symbol

Must be fixed to 001

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

b2 b1 b0

CKDIR

SMD1

SMD0

Serial I/O mode select bit

SMD2

Internal/external clock

select bit

STPS

PRY

PRYE

IOPOL

Parity enable bit

0 : Internal clock

1 : External clock

Stop bit length select bit

Odd/even parity select bit

TxD, RxD I/O polarity

reverse bit

0 : One stop bit

1 : Two stop bits

0 : Parity disabled

1 : Parity enabled

0 : No reverse

1 : Reverse

Usually set to “0”

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

b2 b1 b0

0 : Internal clock

1 : External clock

Invalid

Valid when bit 6 = “1”

0 : Odd parity

1 : Even parity

Invalid

0 : No reverse

1 : Reverse

Usually set to “0”

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

UART0 transmit/receive mode register

Symbol

Address

When reset

U0MR

03A016

0016

Bit name

Bit

symbol

Must be fixed to 001

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

b2 b1 b0

CKDIR

SMD1

SMD0

Serial I/O mode select bit

SMD2

Internal/external clock

select bit

STPS

PRY

PRYE

SLEP

Parity enable bit

0 : Internal clock

1 : External clock

Stop bit length select bit

Odd/even parity select bit

Sleep select bit

0 : One stop bit

1 : Two stop bits

0 : Parity disabled

1 : Parity enabled

0 : Sleep mode deselected

1 : Sleep mode selected

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

b2 b1 b0

0 : Internal clock

1 : External clock

Invalid

Valid when bit 6 = “1”

0 : Odd parity

1 : Even parity

Invalid

Must always be set to “0”

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

Figure 2.11.7 UART0 transmit/receive mode register

Figure 2.11.8 UART2 transmit/receive mode register

M306V2EEFS 数据表(PDF) 104 Page - Renesas Technology Corp

M306V2EEFS 数据表(HTML) 104 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

M306V2EEFS 数据表(PDF) 104 Page - Renesas Technology Corp

M306V2EEFS 数据表(HTML) 104 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载