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M306V2EEFS 数据表(PDF) 102 Page - Renesas Technology Corp |
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M306V2EEFS 数据表(HTML) 102 Page - Renesas Technology Corp |
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102 / 271 page  Rev.1.40 Oct 06, 2004 page 102 of 269 M306V2ME-XXXFP, M306V2EEFP SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART(7 bits) UART (9 bits) Clock synchronous type Clock synchronous type Data bus low-order bits TxD2 UART2 transmit register PAR disabled PAR enabled D8 D7 D6 D5 D4 D3 D2 D1 D0 UART2 transmit buffer register UART (8 bits) UART (9 bits) Clock synchronous type UART2 receive buffer register UART2 receive register 2SP 1SP UART (7 bits) UART (8 bits) UART(7 bits) UART (9 bits) Clock synchronous type Clock synchronous type RxD2 UART (8 bits) UART (9 bits) Address 037E16 Address 037F16 Address 037A16 Address 037B16 Data bus high-order bits D7 D6 D5 D4 D3 D2 D1 D0 D8 00 00000 SP SP PAR “0” Reverse No reverse Error signal output circuit RxD data reverse circuit Error signal output enable Error signal output disable Reverse No reverse Logic reverse circuit + MSB/LSB conversion circuit Logic reverse circuit + MSB/LSB conversion circuit PAR enabled PAR disabled UART Clock synchronous type TxD data reverse circuit SP: Stop bit PAR: Parity bit Figure 2.11.3 Block diagram of UART2 transmit/receive unit |
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