M306V2EEFS datasheet(109/271 Pages) RENESAS

109 / 271 page

Rev.1.40

Oct 06, 2004 page 109 of 269

M306V2ME-XXXFP, M306V2EEFP

Item

Specification

Transfer data format

• Transfer data length: 8 bits

Transfer clock

• When internal clock is selected (bit 3 at addresses 03A016, 037816 = “0”) :

fi/ 2(n+1) (Note 1)

fi = f1, f8, f32

• When external clock is selected (bit 3 at addresses 03A016, 037816 = “1”) :

Input from CLKi pin

Transmission/reception control

_______

• CTS function/RTS function/CTS, RTS function chosen to be invalid

Transmission start condition

• To start transmission, the following requirements must be met:

_ Transmit enable bit (bit 0 at addresses 03A516, 037D16) = “1”

_ Transmit buffer empty flag (bit 1 at addresses 03A516, 037D16) = “0”

_______

_ When CTS function selected, CTS input level = “L”

• Furthermore, if external clock is selected, the following requirements must

also be met:

_ CLKi polarity select bit (bit 6 at addresses 03A416, 037C16) = “0”:

CLKi input level = “H”

_ CLKi polarity select bit (bit 6 at addresses 03A416, 037C16) = “1”:

CLKi input level = “L”

Reception start condition

• To start reception, the following requirements must be met:

_ Receive enable bit (bit 2 at addresses 03A516, 037D16) = “1”

_ Transmit enable bit (bit 0 at addresses 03A516, 037D16) = “1”

_ Transmit buffer empty flag (bit 1 at addresses 03A516, 037D16) = “0”

• Furthermore, if external clock is selected, the following requirements must

also be met:

_ CLKi polarity select bit (bit 6 at addresses 03A416, 037C16) = “0”:

CLKi input level = “H”

_ CLKi polarity select bit (bit 6 at addresses 03A416, 037C16) = “1”:

CLKi input level = “L”

• When transmitting

_ Transmit interrupt cause select bit (bit 0 at address 03B016, bit 4 at

address 037D16) = “0”: Interrupts requested when data transfer from UARTi

transfer buffer register to UARTi transmit register is completed

_ Transmit interrupt cause select bit (bit 0 at address 03B016, bit 4 at

address 037D16) = “1”: Interrupts requested when data transmission from

UARTi transfer register is completed

• When receiving

_ Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

Error detection

• Overrun error (Note 2)

This error occurs when the next data is ready before contents of UARTi

receive buffer register are read out

2.11.2 Clock Synchronous Serial I/O Mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 2.11.2

and 2.11.3 list the specifications of the clock synchronous serial I/O mode. Figures 2.11.15 and 2.11.16

show the UARTi transmit/receive mode register in clock synchronous serial I/O mode.

Interrupt request

generation timing

Table 2.11.2 Specifications of clock synchronous serial I/O mode (1)

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