M306V2EEFS datasheet(112/271 Pages) RENESAS

112 / 271 page

Rev.1.40

Oct 06, 2004 page 112 of 269

M306V2ME-XXXFP, M306V2EEFP

Table 2.11.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note

that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin

outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.)

Table 2.11.4 Input/output pin functions in clock synchronous serial I/O mode

Pin name

Function

Method of selection

TxDi

(P63, P70)

Serial data output

Serial data input

Transfer clock output

Transfer clock input

Programmable I/O port

(Outputs dummy data when performing reception only)

RxDi

(P62, P71)

CLKi

(P61, P72)

Internal/external clock select bit (bit 3 at address 03A0 16, 037816) = “0”

Internal/external clock select bit (bit 3 at address 03A0 16, 037816) = “1”

Port P61 and P72 direction register (bits 1 at address 03EE 16,

bit 2 at address 03EF 16) = “0”

Port P62 and P71 direction register (bits 2 at address 03EE 16,

bit 1 at address 03EF 16)= “0”

(Can be used as an input port when performing transmission only)

CTS/RTS disable bit (bit 4 at address 03A4 16, 037C16) =“0”

CTS/RTS function select bit (bit 2 at addresses 03A4 16, 037C16) = “0”

Port P60 and P73 direction register (bits 0 at address 03EE 16,

bit 3 at address 03EF 16) = “0”

CTS/RTS disable bit (bit 4 at address 03A4 16, 037C16) = “0”

CTS/RTS function select bit (bit 2 at address 03A4 16, 037C16) = “1”

CTS/RTS disable bit (bit 4 at address 03A4 16, 037C16) = “1”

CTS input

RTS output

CTSi/RTSi

(P60, P73)

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