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M306V2EEFS 数据表(PDF) 115 Page - Renesas Technology Corp |
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M306V2EEFS 数据表(HTML) 115 Page - Renesas Technology Corp |
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115 / 271 page  Rev.1.40 Oct 06, 2004 page 115 of 269 M306V2ME-XXXFP, M306V2EEFP (3) Continuous receive mode If the continuous receive mode enable bit (bits 2 at address 03B016, bit 5 at address 037D16) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (4) Serial data logic switch function (UART2) When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 2.11.20 shows the example of serial data logic switch timing. Figure 2.11.20 Serial data logic switch timing D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Transfer clock TxD2 (no reverse) TxD2 (reverse) “H” “L” “H” “L” “H” “L” •When LSB first |
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