M306V2EEFS datasheet(116/271 Pages) RENESAS

116 / 271 page

Rev.1.40

Oct 06, 2004 page 116 of 269

M306V2ME-XXXFP, M306V2EEFP

Item

Specification

Transfer data format

• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

• Start bit: 1 bit

• Parity bit: Odd, even, or nothing as selected

• Stop bit: 1 bit or 2 bits as selected

Transfer clock

• When internal clock is selected (bit 3 at addresses 03A016, 037816 = “0”) :

fi/16(n+1) (Note 1) fi = f1, f8, f32

• When external clock is selected (bit 3 at addresses 03A016, 037816 =“1”) :

fEXT/16(n+1)(Note 1) (Note 2)

Transmission/reception control

_______

• CTS function/RTS function/CTS, RTS function chosen to be invalid

Transmission start condition

• To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 at addresses 03A516, 037D16) = “1”

- Transmit buffer empty flag (bit 1 at addresses 03A516, 037D16) = “0”

_______

- When CTS function selected, CTS input level = “L”

Reception start condition

• To start reception, the following requirements must be met:

- Receive enable bit (bit 2 at addresses 03A516, 037D16) = “1”

- Start bit detection

Interrupt request

• When transmitting

generation timing

- Transmit interrupt cause select bits (bits 0 at address 03B016, bit4 at

address 037D16) = “0”: Interrupts requested when data transfer from UARTi

transfer buffer register to UARTi transmit register is completed

- Transmit interrupt cause select bits (bits 0 at address 03B016, bit4 at

address 037D16) = “1”: Interrupts requested when data transmission from

UARTi transfer register is completed

•

When receiving

- Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

Error detection

• Overrun error (Note 3)

This error occurs when the next data is ready before contents of UARTi

receive buffer register are read out

• Framing error

This error occurs when the number of stop bits set is not detected

• Parity error

This error occurs when if parity is enabled, the number of 1’s in parity and

character bits does not match the number of 1’s set

• Error sum flag

This flag is set (= 1) when any of the overrun, framing, and parity errors is

encountered

2.11.3 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer

data format. Tables 2.11.5 and 2.11.6 list the specifications of the UART mode. Figure 2.11.21 and

2.11.22 show the UARTi transmit/receive mode register in UART mode.

Table 2.11.5 Specifications of UART Mode (1)

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