H8SSLASH2218 datasheet(332/750 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 284 of 698

REJ09B0074-0600

9.3.3

Timer I/O Control Register (TIOR)

The TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for

channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the

TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST

bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the

counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this

setting is invalid and the register operates as a buffer register.

• TIORH_0, TIOR_1, TIOR_2

Bit

Bit Name Initial value

R/W

Description

IOB3

IOB2

IOB1

IOB0

R/W

I/O Control B3 to B0

Specify the function of TGRB.

IOA3

IOA2

IOA1

IOA0

R/W

I/O Control A3 to A0

Specify the function of TGRA.

• TIORL_0

Bit

Bit Name Initial value

R/W

Description

IOD3

IOD2

IOD1

IOD0

R/W

I/O Control D3 to D0

Specify the function of TGRD.

IOC3

IOC2

IOC1

IOC0

R/W

I/O Control C3 to C0

Specify the function of TGRC.

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