H8SSLASH2218 datasheet(330/750 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 282 of 698

REJ09B0074-0600

Table 9.7

TPSC2 to TPSC0 (channel 2)

Bit 2

Bit 1

Bit 0

Channel

TPSC2

TPSC1

TPSC0

Description

Internal clock: counts on

φ/1

Internal clock: counts on

φ/4

Internal clock: counts on

φ/16

Internal clock: counts on

φ/64

External clock: counts on TCLKA pin input

External clock: counts on TCLKB pin input

External clock: counts on TCLKC pin input

Internal clock: counts on

φ/1024

Note:

This setting is ignored when channel 1 is in phase counting mode.

9.3.2

Timer Mode Register (TMDR)

The TMDR registers are used to set the operating mode for each channel. The TPU has three

TMDR registers, one for each channel. TMDR register settings should be made only when TCNT

operation is stopped.

Bit

Bit Name

Initial value

R/W

Description

7, 6

—

All 1

—

Reserved

These bits are always read as 1 and cannot be modified.

BFB

R/W

Buffer Operation B

Specifies whether TGRB is to operate in the normal way,

or TGRB and TGRD are to be used together for buffer

operation. When TGRD is used as a buffer register.

TGRD input capture/output compare is not generation. In

channels 1 and 2, which have no TGRD, bit 5 is reserved.

It is always read as 0 and cannot be modified.

0: TGRB operates normally

1: TGRB and TGRD used together for buffer operation

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