H8SSLASH2218 datasheet(327/750 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 279 of 698

REJ09B0074-0600

9.3.1

Timer Control Register (TCR)

The TCR registers control the TCNT operation for each channel. The TPU has a total of three TCR

registers, one for each channel (channel 0 to 2). TCR register settings should be made only when

TCNT operation is stopped.

Bit

Bit Name Initial value

R/W

Description

CCLR2

CCLR1

CCLR0

R/W

Counter Clear 2 to 0

These bits select the TCNTcounter clearing source. See

tables 9.3 and 9.4 for details.

CKEG1

CKEG0

R/W

Clock Edge 1 and 0

These bits select the input clock edge. When the internal

clock is counted using both edges, the input clock

frequency is halved (e.g.,

φ/4 both edges = φ/2 rising

edge). If phase counting mode is used on channels 1, 2,

4, and 5, this setting is ignored and the phase counting

mode setting has priority. Internal clock edge selection is

valid when the input clock is

φ/4 or slower. If φ/1 is

selected as the input clock, this setting is ignored and

count at falling edge of

φ is selected.

00: Count at rising edge

01: Count at falling edge

×: Count at both edges

Legend:

×: Don’t care

TPSC2

TPSC1

TPSC0

R/W

Time Prescaler 2 to 0

These bits select the TCNT counter clock. The clock

source can be selected independently for each channel.

See tables 9.5 to 9.7 for details.

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