H8SSLASH2218 datasheet(430/750 Pages) RENESAS

430 / 750 page

Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 382 of 698

REJ09B0074-0600

Bit

Bit Name Initial Value R/W

Description

PER

R/(W)* Parity Error

Indicates that a parity error occurred during reception

using parity addition in asynchronous mode, causing

abnormal termination.

[Setting condition]

• When a parity error is detected during reception

If a parity error occurs, the receive data is transferred

to RDR but the RDRF flag is not set. Also, subsequent

serial reception cannot be continued while the PER

flag is set to 1. In clocked synchronous mode, serial

transmission cannot be continued, either.

[Clearing condition]

• When 0 is written to PER after reading PER = 1

The PER flag is not affected and retains its previous

state when the RE bit in SCR is cleared to 0.

TEND

Transmit End

This bit is set to 1 when no error signal has been sent

back from the receiving end and the next transmit data is

ready to be transferred to TDR.

[Setting conditions]

• When the TE bit in SCR is 0 and the ERS bit is also 0

• When the ERS bit is 0 and the TDRE bit is 1 after the

specified interval following transmission of 1-byte data.

The timing of bit setting differs according to the register

setting as follows:

When GM = 0 and BLK = 0, 12.5 etu after transmission

starts

When GM = 0 and BLK = 1, 11.5 etu after transmission

starts

When GM = 1 and BLK = 0, 11.0 etu after transmission

starts

When GM = 1 and BLK = 1, 11.0 etu after transmission

starts

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DMAC is activated by a TXI interrupt and

transfers transmission data to TDR

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