H8SSLASH2218 datasheet(427/750 Pages) RENESAS

427 / 750 page

Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 379 of 698

REJ09B0074-0600

Bit

Bit Name Initial Value

R/W

Description

PER

R/(W)* Parity Error

[Setting condition]

• When a parity error is detected during reception

If a parity error occurs, the receive data is transferred

to RDR but the RDRF flag is not set. Also,

subsequent serial reception cannot be continued

while the PER flag is set to 1. In clocked

synchronous mode, serial transmission cannot be

continued, either.

[Clearing condition]

• When 0 is written to PER after reading PER = 1

The PER flag is not affected and retains its previous

state when the RE bit in SCR is cleared to 0.

TEND

Transmit End

[Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of a 1-

byte serial transmit character

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DMAC is activated by a TXI interrupt and

writes data to TDR

MPB

Multiprocessor Bit

MPB stores the multiprocessor bit in the receive data.

When the RE bit in SCR is cleared to 0 its previous state

is retained. This bit retains its previous state when the

RE bit in SCR is cleared to 0.

MPBT

R/W

Multiprocessor Bit Transfer

MPBT stores the multiprocessor bit to be added to the

transmit data.

Note:* The write value should always be 0 to clear the flag.

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