H8SSLASH2218 datasheet(424/750 Pages) RENESAS

424 / 750 page

Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 376 of 698

REJ09B0074-0600

Bit

Bit Name Initial Value

R/W

Description

MPIE

R/W

Multiprocessor Interrupt Enable (enabled only when the MP

bit in SMR is 1 in asynchronous mode)

Write 0 to this bit in Smart Card interface mode.

When receive data including MPB = 0 is received, receive

data transfer from RSR to RDR, receive error detection,

and setting of the RERF, FER, and ORER flags in SSR,

are not performed.

When receive data including MPB = 1 is received, the MPB

bit in SSR is set to 1, the MPIE bit is cleared to 0

automatically, and generation of RXI and ERI interrupts

(when the TIE and RIE bits in SCR are set to 1) and FER

and ORER flag setting are enabled.

TEIE

R/W

Transmit End Interrupt Enable

Write 0 to this bit in Smart Card interface mode.

TEI cancellation can be performed by reading 1 from the

TDRE flag in SSR, then clearing it to 0 and clearing the

TEND flag to 0, or clearing the TEIE bit to 0.

CKE1

CKE0

R/W

Clock Enable 0 and 1

Enables or disables clock output from the SCK pin. The

clock output can be dynamically switched in GSM mode.

For details, refer to section 12.7.9, Clock Output Control.

When the GM bit in SMR is 0:

00: Output disabled (SCK pin can be used as an I/O port

pin)

01: Clock output

×: Reserved

When the GM bit in SMR is 1:

00: Output fixed low

01: Clock output

10: Output fixed high

11: Clock output

Legend:

×: Don’t care

H8S/2218 数据表(PDF) 424 Page - Renesas Technology Corp

H8S/2218 数据表(HTML) 424 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载