H8SSLASH2218 datasheet(421/750 Pages) RENESAS

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Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 373 of 698

REJ09B0074-0600

12.3.6

Serial Control Register (SCR)

SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also

used to selection of the transfer clock source. For details on interrupt requests, refer to section

12.9, Interrupts. Some bits in SCR have different functions in normal mode and smart card

interface mode.

• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)

Bit

Bit Name Initial Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When this bit is set to 1, the TXI interrupt request is

enabled.

TXI interrupt request cancellation can be performed by

reading 1 from the TDRE flag, then

clearing it to 0, or clearing the TIE bit to 0.

RIE

R/W

Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests

are enabled.

RXI and ERI interrupt request cancellation can be

performed by reading 1 from the RDRF flag, or the FER,

PER, or ORER flag, then clearing the flag to 0, or

clearing the RIE bit to 0.

R/W

Transmit Enable

When this bit s set to 1, transmission is enabled.

In this state, serial transmission is started when transmit

data is written to TDR and the TDRE flag in SSR is

cleared to 0. SMR setting must be performed to decide

the transfer format before setting the TE bit to 1. The

TDRE flag in SSR is fixed at 1 if transmission is disabled

by clearing this bit to 0.

R/W

Receive Enable

When this bit is set to 1, reception is enabled.

Serial reception is started in this state when a start bit is

detected in asynchronous mode or serial clock input is

detected in clocked synchronous mode. SMR setting

must be performed to decide the transfer format before

setting the RE bit to 1.

Clearing the RE bit to 0 does not affect the RDRF, FER,

PER, and ORER flags, which retain their states.

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