H8SSLASH2218 datasheet(521/750 Pages) RENESAS

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Section 14 Universal Serial Bus (USB)

Rev.6.00 Jun. 03, 2008 Page 473 of 698

REJ09B0074-0600

14.3.4

USB Trigger Register 0 (UTRG0)

UTRG0 is a one-shot register to generate triggers to the FIFO for each endpoint EP0 to EP3. For

details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.

Bit

Bit Name

Initial Value

R/W

Description

7, 6

—

All 0

Reserved

These bits are always read as 0 and cannot be

modified.

EP2RDFN

EP2 Read Complete

0: Performs no operation.

1: Writes 1 to this bit after reading data for EP2 OUT

FIFO. EP2 has a dual-FIFO configuration. This

trigger is generated to the currently effective FIFO.

EP1PKTE

EP1 Packet Enable

0: Performs no operation.

1: Generates a trigger to enable the transmission to

EP1 IN FIFO. EP1 has a dual-FIFO configuration.

This trigger is generated to the currently effective

FIFO.

EP3PKTE

EP3 Packet Enable

0: Performs no operation.

1: Generates a trigger to enable the transmission to

EP3 IN FIFO.

EP0oRDFN 0

EP0o Read Complete

0: Performs no operation.

1: Writes 1 to this bit after reading data for EP0o OUT

FIFO. This trigger enables EP0o to receive the

next packet.

EP0iPKTE

EP0i Packet Enable

0: Performs no operation.

1: Generates a trigger to enable the transmission to

EP0i IN FIFO.

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