H8SSLASH2218 datasheet(576/750 Pages) RENESAS

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Section 14 Universal Serial Bus (USB)

Rev.6.00 Jun. 03, 2008 Page 528 of 698

REJ09B0074-0600

14.8.4

Setup Data Reception

The following must be noted for the EP0s FIFO used to receive 8-byte setup data. The USB is

designed to always receive setup commands. Accordingly, write from the UDC has higher priority

than read from the LSI. If the reception of the next setup command starts while the LSI is reading

data after completing reception, this data read from the LSI is forcibly cancelled and the next setup

command write starts. After the next setup command write, data read from the LSI is thus

undefined. Read operation is forcibly disabled because data cannot be guaranteed if DP-RAM used

as FIFO accesses the same address for write and read.

14.8.5

FIFO Clear

If the USB cable is disconnected during communication, old data may be contained in the FIFO.

Accordingly, FIFOs must be cleared immediately after USB cable connection. In addition, after

bus reset, all FIFOs must also be cleared. Note, however, that FIFOs that are currently used for

data transfer to or from the host must not be cleared.

14.8.6

IRQ6 Interrupt

A suspend/resume interrupt requested by

IRQ6 must be specified as falling-edge sensitive.

14.8.7

Data Register Overread or Overwrite

When the CPU reads or writes to data registers, the following must be noted:

• Transmit data registers (UEDR0i, UEDR3, UEDR1)

Data to be written to the transmit data registers must be within the maximum packet size. For

the transmit data register of EP1 having a dual-FIFO configuration, data to be written at any

time must be within the maximum packet size. In this case, after a data write, the FIFO is

switched to the other FIFO, enabling an further data write, when the PKTE bit in UTRG0 is set

to 1. Accordingly, data of size corresponding to two FIFOs must not be written to the transmit

data registers at a time.

• Receive data registers (UEDR0o, UEDR2)

Receive data registers must not read a data size that is greater than the effective size of the read

data item. In other words, receive data registers must not read data with data size larger than

that specified by the receive data size register. For the receive data register of EP2 having a

dual-FIFO configuration, data to be read at any time must be within the maximum packet size.

In this case, after reading the currently selected FIFO, set the RDFN bit in UTRG to 1. This

switches the FIFO to the other FIFO and updates the receive data size, enabling the next data

read. In addition, if there is no receive data in a FIFO, data must not be read. Otherwise, the

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