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H8S/2218 数据表(PDF) 578 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 578 Page - Renesas Technology Corp |
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578 / 750 page ![]() Section 14 Universal Serial Bus (USB) Rev.6.00 Jun. 03, 2008 Page 530 of 698 REJ09B0074-0600 14.8.10 Level Shifter for VBUS and IRQx Pins The VBUS and IRQx pins of this USB module must be connected to the USB connector’s VBUS pin via a level shifter. This is because the USB module has a circuit that operates by detecting USB cable connection or disconnection. Even if the power of the device incorporating this USB module is turned off, 5-V power is applied to the USB connector’s VBUS pin while the USB cable is connected to the device set. To protect the LSI from destruction, use a level shifter such as the HD74LV-A Series, which allows voltage application to the pin even when the power is off. 14.8.11 USB Endpoint Data Read and Write To write data to an USB endpoint data register (UEDR0i, UEDR1, or UEDR3) on the transmit side using a CPU word or longword transfer instruction, the size of data to be written must be smaller than the size of data that is to be transmitted. For example, when 7-byte data is transferred to the host, 8-byte data is sent to the host if data is written twice by the longword transfer instructions or if data is written four times by the word transfer instructions. To write 7-byte data correctly, data must be written once by a longword transfer instruction, once by a word transfer instruction, and once by a byte transfer instruction, or data must be written three times by a word transfer instruction and once by a byte transfer instruction. To read data from the USB endpoint data register (UEDR0o or UEDR2) on the receive side, the correct size of data must be read. In this case, the data size is specified by the USB endpoint receive size register (UESZ0o or UESZ2). To execute DMA transfer on data in the USB endpoint data register using the on-chip DMAC, byte transfer musts be used. In word transfer, odd-byte data cannot be transferred. Word transfer is thus disabled. 14.8.12 Restrictions on Entering and Canceling Power-Down Mode Before entering the power-down mode, set the USB module stop 2 state. The UDC core must not be reset. To access the USB module after canceling power-down mode, cancel the USB module stop 2 state and wait for the USB operating clock (48 MHz) stabilization time. |
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