H8SSLASH2218 datasheet(588/750 Pages) RENESAS

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Section 15 A/D Converter

Rev.6.00 Jun. 03, 2008 Page 540 of 698

REJ09B0074-0600

15.3.3

A/D Control Register (ADCR)

The ADCR enables A/D conversion started by an external trigger signal.

Bit

Bit Name Initial Value

R/W

Description

TRGS1

TRGS0

R/W

Timer Trigger Select 1 and 0

Enables the start of A/D conversion by a trigger signal.

Only set bits TRGS1 and TRGS0 while conversion is

stopped (ADST = 0).

00: A/D conversion start by software

01: A/D conversion start by TPU

10: Setting prohibited

11: A/D conversion start by external trigger pin

(

ADTRG)

5, 4

—

All 1

—

Reserved

These bits are always read as 1 cannot be modified.

CKS1

CKS0

R/W

Clock Select 1 and 0

These bits specify the A/D conversion time. The

conversion time should be changed only when ADST =

00:

Conversion time = 530 states (Max.)

01:

Conversion time = 266 states (Max.)

10:

Conversion time = 134 states (Max.)

11:

Conversion time = 68 states (Max.)

The conversion time setting should exceed the

conversion time shown in section 22.6, A/D Converter

Characteristics.

1, 0

—

All 1

—

Reserved

These bits are always read as 1, and only 1 should be

written to them.

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