H8SSLASH2218 datasheet(616/750 Pages) RENESAS

616 / 750 page

Section 17 Flash Memory (F-ZTAT Version)

Rev.6.00 Jun. 03, 2008 Page 568 of 698

REJ09B0074-0600

RxD2

TxD2

SCI_2

This LSI

Flash memory

Write data reception

Note: * Mode pin and FWE pin input must satisfy the mode programming setup time (t

MDS = 200ns)

with respect to the reset release timing.

Legend:

× : Don’t care

FWE

MD2 to MD0*

Verify data transmission

Host

On-chip RAM

0EMLE

Figure 17.7 System Configuration in SCI Boot Mode

Table 17.4 shows the boot mode operations between reset end and branching to the programming

control program.

1. When boot mode is used, the flash memory programming control program must be prepared in

the host beforehand. Prepare a programming control program in accordance with the

description in section 17.8, Flash Memory Programming/Erasing. In boot mode, if any data has

been programmed into the flash memory (if all data is not 1), all flash memory blocks are

erased. Boot mode is for use in enforced exit when user program mode is unavailable, such as

the first time on-board programming is performed, or if the program activated in user program

mode is accidentally erased.

2. The SCI_2 should be set to asynchronous mode, and the transfer format as follows: 8-bit data,

1 stop bit, and no parity.

3. When the boot program is initiated, the chip measures the low-level period of asynchronous

SCI communication data (H'00) transmitted continuously from the host. The chip then

calculates the bit rate of transmission from the host, and adjusts the SCI_2 bit rate to match that

of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be

pulled up on the board if necessary. After the reset ends, it takes approximately 100 states

before the chip is ready to measure the low-level period.

4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the end of

bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has

been received normally, and transmit one H'55 byte to the chip. If reception could not be

performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit

rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of

the host and the chip. To operate the SCI properly, set the host’s transfer bit rate and system

clock frequency of this LSI within the ranges listed in table 17.5.

H8S/2218 数据表(PDF) 616 Page - Renesas Technology Corp

H8S/2218 数据表(HTML) 616 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载