H8SSLASH2218 datasheet(650/750 Pages) RENESAS

650 / 750 page

Section 19 Clock Pulse Generator

Rev.6.00 Jun. 03, 2008 Page 602 of 698

REJ09B0074-0600

Table 19.4

External Clock Input Conditions when Duty Adjustment Circuit Is not Used

Item

Symbol

min

max

Min

max

min

max

Unit

Test

Conditions

External clock input low pulse width

tEXL

—

31.25

—

20.8

—

Figure 19.5

External clock input high pulse width

tEXH

—

31.25

—

20.8

—

External clock rise time

tEXr

—

6.25

—

5.25

External clock fall time

tEXf

—

6.25

—

5.25

EXH

EXL

EXr

EXf

CC × 0.5

EXTAL

Figure 19.5 External Clock Input Timing

19.3

Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty

cycle of the clock signal from the oscillator to generate the system clock (

φ).

19.4

Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock to generate

φ/2, φ/4, φ/8, φ/16, and φ/32.

19.5

Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the clock supplied to the bus master by setting the

bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from high-speed mode, or

medium-speed clocks (

φ/2, φ/4, φ/8, φ/16, φ/32).

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