H8SSLASH2218 datasheet(666/750 Pages) RENESAS

666 / 750 page

Section 20 Power-Down Modes

Rev.6.00 Jun. 03, 2008 Page 618 of 698

REJ09B0074-0600

Figure 20.3 shows the timing for transition to and clearance of medium-speed mode.

Note: *

Supported only by the H8S/2218 Group.

SCKCR

φ,

supporting module clock

Bus master clock

Internal address bus

Internal write signal

Medium-speed mode

Figure 20.3 Medium-Speed Mode Transition and Clearance Timing

20.3

Sleep Mode

20.3.1

Transition to Sleep Mode

When the SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in

LPWRCR are cleared to 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops

but the contents of the CPU's internal registers are retained. Other supporting modules do not stop.

20.3.2

Exiting Sleep Mode

Sleep mode is exited by any interrupt, or signals at the

RES, MRES*, or STBY pin.

• Exiting Sleep Mode by Interrupts

When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep

mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the

CPU.

• Exiting Sleep Mode by RES or MRES* Pin

Setting the

RES or MRES* pin level Low selects the reset state. After the stipulated reset input

duration, driving the

RES or MRES* pin High starts the CPU performing reset exception

processing.

• Exiting Sleep Mode by STBY Pin

When the

STBY pin level is driven Low, a transition is made to hardware standby mode.

Note: *

Supported only by the H8S/2218 Group.

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