H8SSLASH2218 datasheet(670/750 Pages) RENESAS

670 / 750 page

Section 20 Power-Down Modes

Rev.6.00 Jun. 03, 2008 Page 622 of 698

REJ09B0074-0600

20.5.3

Hardware Standby Mode Timing

Figure 20.5 shows an example of hardware standby mode timing.

When the

STBY pin is driven low after the RES pin has been driven low, a transition is made to

hardware standby mode. Hardware standby mode is cleared by driving the

STBY pin high, waiting

for the oscillation stabilization time, then changing the

RES pin from low to high.

Oscillator

RES

STBY

Oscillation

stabilization

time tOSC1

Reset exception

handling

Figure 20.5 Hardware Standby Mode Timing (Example)

20.5.4

Hardware Standby Mode Timings

Timing of Transition to Hardware Standby Mode:

1. To retain RAM contents with the RAME bit set to 1 in SYSCR

Drive the

RES signal low at least 10 states before the STBY signal goes low, as shown in

figure 20.6. After

STBY has gone low, RES has to wait for at least 0 ns before becoming high.

≥ 0 ns

≥ 10 tcyc

STBY

RES

Figure 20.6 Timing of Transition to Hardware Standby Mode

2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do

not need to be retained

RES does not have to be driven low as in the above case.

H8S/2218 数据表(PDF) 670 Page - Renesas Technology Corp

H8S/2218 数据表(HTML) 670 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载